Michael Graf

Protective circuit against electrostatic discharges

Device and method for detecting a number of electrostatic discharges

Low leakage FINFETs

Method and system for incorporating high voltage devices in an EEPROM

Semiconductor array and method for manufacturing a semiconductor array

DMOS DEVICE WITH SEALED CHANNEL PROCESSING

Electrostatic discharge (ESD) protection structure and a circuit using the same

Method for producing a semiconductor arrangement, semiconductor arrangement and its application

Method for producing deep trench structures

High-voltage field-effect transistor

Lateral DMOS transistor and method for the production thereof

Method and manufacturing low leakage MOSFETs and FinFETs

DMOS device with sealed channel processing

REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS

Semiconductor array and method for manufacturing a semiconductor array

DMOS transistor with optimized periphery structure

Electrostatic discharge (ESD) protection structure and a circuit using the same

Method and system for incorporating high voltage devices in an EEPROM

Registration mark within an overlap of dopant regions

Method for manufacturing a metal-semiconductor contact in semiconductor components

Integrated circuit and method for manufacturing an integrated circuit

ESD protection circuit with scalable current capacity and voltage capacity

Method of producing active semiconductor layers of different thicknesses in an SOI wafer

Process for manufacturing vertically insulated structural components on SOI material of various thickness