Vivek Sarda

FSYNC MISMATCH TRACKING

MAINTAINING A VIRTUAL TIME OF DAY

MAINTAINING THE CORRECT TIME WHEN COUNTER VALUES ARE TRANSFERRED BETWEEN CLOCK DOMAINS

FSYNC mismatch tracking

Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal

Secondary phase compensation assist for PLL IO delay

Signal delay control using a recirculating delay loop and a phase interpolator

Data protocol over clock line

FSYNC mismatch tracking

Maintaining the correct time when counter values are transferred between clock domains

Maintaining a virtual time of day

Signal delay control using a recirculating delay loop and a phase interpolator

Data protocol over clock line

Phase transport with frequency translation without a PLL

FSYNC mismatch tracking

Secondary phase compensation assist for PLL IO delay

Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal

Phase transport with frequency translation without a PLL

Clock skew detection and management

Data handoff between two clock domains sharing a fundamental beat

Maintaining the correct time when counter values are transferred between clock domains

Delay adjustment using frequency estimation

Adaptive jitter and spur adjustment for clock circuits

Failsafe clock product using frequency estimation

Transition scan coverage for cross clock domain logic

Regulator control during scan shift and capture cycles

High frequency synthesis and duty cycle control with interpolative dividers using a low speed interface

Digital fast lock for phase-locked loops

Receiver Circuits and Systems for Receiving Medium Wave and Short Wave Signals

Frequency adjustment for clock generator

Multimode, multiline data transfer system and method of operating the same