Thomas A. Volpe

Systolic array with output rounding across multiple data streams

Multi-level action lookup table for dynamic throttling adjustments

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

Monitoring a software-based activity monitor that configures the throttling of a hardware-based activity monitor

On-circuit activity monitoring for modifying integrated circuit processing

On-circuit utilization monitoring for a systolic array

Extending virtual routing and forwarding

Processor with control flow

Early semaphore update

On-chip software-based activity monitor to configure throttling at a hardware-based activity monitor

Simulating network packets in a packet processing pipeline

Testing computer networks in real time

Multiple accumulate busses in a systolic array

Processing for multiple input data sets in a multi-layer neural network

Semiconductor package with capacitance die

Processing for multiple input data sets

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

Systolic array with efficient input reduction and extended array performance

Independently configurable access device stages for processing interconnect access requests

Dynamically configurable networking device interfaces for directional capacity modifications

Arbitrating throttling recommendations for a systolic array

Multiple accumulate busses in a systolic array

Collecting statistics for persistent memory

Independently configurable interleaving for interconnect access requests

Alternative interrupt reporting channels for microcontroller access devices

DATA-TYPE-AWARE CLOCK-GATING

Increasing positive clock skew for systolic array critical path

Powering-down or rebooting a device in a system fabric

Tracking persistent memory usage

Multiple accumulate busses in a systolic array

Multiple busses interleaved in a systolic array

Event-based device performance monitoring

Parallelism within a systolic array using multiple accumulate busses

Independently configurable remapping for interconnect access requests

Generating programmatically defined fields of metadata for network packets

Systolic array component combining multiple integer and floating-point data types

Integrated packet generator and checker

Notifications in integrated circuits

Credit mechanisms for packet policing

Pattern generation using a direct memory access engine

Communication of data between software applications

Performance debug for networks

Multi-stage counters

Reducing dynamic power consumption in arrays

Address translation and address translation memory for storage class memory

Reconfigurable instruction

Instruction memory

Powering-down or rebooting a device in a system fabric

Page table search engine

Address translation for storage class memory in a system that includes virtual machines

Indexing a memory region

Collecting statistics for persistent memory

Uniform memory access architecture

External memory protection for content addressable memory

Execution synchronization and tracking

Integrated packet generator and checker

Network device with integrated packet generators or packet checkers

Managing migration events performed by a memory controller

Forwarding action redirection

Extending virtual routing and forwarding

Determining destination resolution stages for forwarding decisions

Performance monitoring for storage-class memory

Testing computer networks in real time

Filtering control plane decision requests for forwarding network packets

Counters for large flow detection

Statistics collecting architecture

Write minimization for de-allocated memory

Write failure handling for a memory controller to non-volatile memory

Load-balanced forwarding of network packets generated by a networking device

Restructuring a multi-dimensional array

Processing for multiple input data sets

Scheduling neural network computations based on memory capacity

Efficient memory management in multi-tenant virtualized environment

Access control based on range-matching

Combined cache-overflow memory structure

Non-recirculating label switching packet processing

Streaming interconnect architecture

Uniform memory access architecture

Unified quality of service (QoS) for label switching traffic

Time-out tracking for high-throughput packet transmission

Pipelined evaluations for algorithmic forwarding route lookup

Network packet tracing

Credit mechanisms for packet policing

Low-latency metadata-based packet rewriter

Multi-stage counters

Device with multiple interrupt reporting modes

Distributed precision time architecture

Reliable precision time architecture

Pipelined evaluations for algorithmic forwarding route lookup

Sampling based on large flow detection for network visibility monitoring

Accessing a memory location using a two-stage hash scheme

Dynamic error correction configuration

Robust fast re-routing for label switching packets

Historically large flows in network visibility monitoring

Congestion control for label switching traffic

Non-recirculating label switching packet processing

Pipelined packet policer

Network visibility monitoring

Large flow detection for network visibility monitoring

Burst absorption for processing network packets