Inventor profile of:

John D. Pape

City:

Cedar Park, Texas

Country:

United States

Published Applications:

19

Last publication date:

2025-10-09

Top Assignees for applications by John D. Pape

The entities that hold a legal rights for patent applications filed by inventor Pape John D.:

Recent patent applications by Pape John D.

John D. Pape from Cedar Park, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-09
US20250315518A1
Physics

Consistent Speculation of Pointer Authentication

#2 | 2025-06-10
US18459203
Physics

Renaming context identifiers in a processor

#3 | 2025-05-08
US20250147767A1
Physics

Processing of Data Synchronization Barrier Instructions

#4 | 2025-03-20
US20250094567A1
Physics

Consistent Speculation of Pointer Authentication

#5 | 2025-03-20
US20250094174A1
Physics

Coprocessor Prefetcher

#6 | 2025-02-18
US17933037
Physics

Processing of data synchronization barrier instructions

#7 | 2024-10-03
US20240329988A1
Physics

Load Instruction Fusion

#8 | 2024-06-11
US17652501
Physics

Load instruction fusion

#9 | 2024-03-21
US20240095037A1
Physics

Coprocessor prefetcher

#10 | 2024-02-13
US17817866
Physics

Stack pointer instruction buffer for zero-cycle loads

#11 | 2023-07-27
US20230236988A1
Physics

Reducing translation lookaside buffer searches for splintered pages

#12 | 2023-03-23
US20230092898A1
Physics

Coprocessor prefetcher

#13 | 2023-01-19
US20230017473A1
Physics

Poison mechanisms for deferred invalidates

#14 | 2022-03-10
US20220075735A1
Physics

Limiting translation lookaside buffer searches using active page size

#15 | 2022-03-10
US20220075734A1
Physics

Reducing translation lookaside buffer searches for splintered pages

#16 | 2022-03-03
US20220066947A1
Physics

Translation lookaside buffer striping for efficient invalidation operations

#17 | 2019-01-24
US20190026040A1
Physics

Acceleration and dynamic allocation of random data bandwidth in multi-core processors

#18 | 2018-06-07
US20180157435A1
Physics

Acceleration and dynamic allocation of random data bandwidth in multi-core processors

#19 | 2010-06-10
US20100146217A1
Physics

Memory interface device and methods thereof

InventorID:

2208844 ⎘