Kiran V. Chatty

Electrostatic discharge (ESD) device and method of fabricating

Vertical NPNP structure in a triple well CMOS process

Field effect transistor with air gap dielectric

Electrostatic discharge power clamp with a JFET based RC trigger circuit

Silicon controlled rectifiers (SCR), methods of manufacture and design structures

Low leakage electrostatic discharge protection circuit

Low trigger voltage electrostatic discharge NFET in triple well CMOS technology

Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure

Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure

BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES

Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure

Robust ESD protection circuit, method and design structure for tolerant and failsafe designs

Electrical overstress protection circuit

Field effect transistor with air gap dielectric

Signal and power supply integrated ESD protection device

On demand circuit function execution employing optical sensing

Methods for forming back-end-of-line resistive semiconductor structures

Back-end-of-line resistive semiconductor structures

Mixed voltage tolerant input/output electrostatic discharge devices

Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory

Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices

Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory

Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations

ELECTROSTATIC DISCHARGE POWER CLAMP WITH IMPROVED ELECTRICAL OVERSTRESS ROBUSTNESS

Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit

Electrostatic discharge (ESD) device and method of fabricating

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

LATERAL JUNCTION BREAKDOWN TRIGGERED SILICON CONTROLLED RECTIFIER BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Method and structure to process thick and thin fins and variable fin to fin spacing

METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING

Semiconductor devices and methods of manufacturing thereof

ESD protection device and method

Method and structure to process thick and thin fins and variable fin to fin spacing

On demand circuit function execution employing optical sensing

High voltage ESD power clamp

VERTICAL SILICON CONTROLLED RECTIFIER ELECTRO-STATIC DISCHARGE PROTECTION DEVICE IN BI-CMOS TECHNOLOGY

Low trigger voltage, low leakage ESD NFET

Integrated circuit amplifier device and method using FET tunneling gate current

High voltage ESD power clamp

Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time

Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing

LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES

MOSFET with decoupled halo before extension

Method and structure to suppress external latch-up

PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS