Inventor profile of:

John Chen

City:

Shanghai

Country:

China

Published Applications:

15

Last publication date:

2013-10-10

Top Assignees for applications by John Chen

The entities that hold a legal rights for patent applications filed by inventor Chen John:

Recent patent applications by Chen John

John Chen from Shanghai, CN has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-10-10
US20130264491A1
Electricity

Method for dual energy implantation for ultra-shallow junction formation of MOS devices

#2 | 2013-05-02
US20130109142A1
Electricity

Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

#3 | 2012-06-28
US20120164803A1
Electricity

STRAINED-INDUCED MOBILITY ENHANCEMENT NANO-DEVICE STRUCTURE AND INTEGRATED PROCESS ARCHITECTURE FOR CMOS TECHNOLOGIES

#4 | 2011-06-16
US20110143512A1
Electricity

Method for dual energy implantation for ultra-shallow junction formation of MOS devices

#5 | 2009-11-26
US20090291550A1
Electricity

Poly gate etch method and device for sonos-based flash memory

#6 | 2009-06-18
US20090152599A1
Electricity

Silicon germanium and polysilicon gate structure for strained silicon transistors

#7 | 2009-03-12
US20090065805A1
Electricity

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

#8 | 2008-07-24
US20080173941A1
Electricity

ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS

#9 | 2008-05-22
US20080119032A1
Electricity

Etching method and structure using a hard mask for strained silicon MOS transistors

#10 | 2007-08-23
US20070196992A1
Electricity

In-situ doped silicon germanium and silicon carbide source drain region for strained silicon CMOS transistors

#11 | 2007-04-05
US20070077716A1
Electricity

Method and structure for second spacer formation for strained silicon MOS transistors

#12 | 2007-03-29
US20070072376A1
Electricity

Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

#13 | 2007-03-22
US20070063221A1
Electricity

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

#14 | 2006-08-31
US20060194395A1
Electricity

Metal hard mask method and structure for strained silicon MOS transistors

#15 | 2005-12-29
US20050287753A1
Electricity

MOS device for high voltage operation and method of manufacture

InventorID:

223236 ⎘