Inventor profile of:

Arjun Kar-Roy

City:

Irvine, California

Country:

United States

Published Applications:

19

Last publication date:

2018-08-30

Top Assignees for applications by Arjun Kar-Roy

The entities that hold a legal rights for patent applications filed by inventor Kar-Roy Arjun:

Recent patent applications by Kar-Roy Arjun

Arjun Kar-Roy from Irvine, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-08-30
US20180247856A1
Electricity

Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

#2 | 2017-11-16
US20170330789A1
Electricity

Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

#3 | 2016-04-28
US20160118339A1
Electricity

Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

#4 | 2016-03-10
US20160069739A1
Physics

Light sensor with chemically resistant and robust reflector stack

#5 | 2015-12-24
US20150368094A1
Performing operations; transporting

Robust MEMS structure with via cap and related method

#6 | 2015-12-24
US20150368092A1
Performing operations; transporting

Scalable self-supported MEMS structure and related method

#7 | 2015-09-15
US11198425
Electricity

Deep N wells in triple well structures

#8 | 2013-05-02
US20130109176A1
Electricity

Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation

#9 | 2012-07-03
US11787063
-

Method for fabricating a backside through-wafer via in a processed wafer and related structure

#10 | 2011-01-27
US20110018109A1
Electricity

Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation

#11 | 2010-08-10
US11724916
-

Deep trench isolation and method for forming same

#12 | 2010-04-27
US11641500
-

Method for fabricating a frontside through-wafer via in a processed wafer and related structure

#13 | 2009-12-03
US20090298285A1
Electricity

Fabricating a top conductive layer in a semiconductor die

#14 | 2009-09-15
US11641925
-

Method for fabricating a top conductive layer in a semiconductor die and related structure

#15 | 2009-05-21
US20090128768A1
Physics

Self-planarized passivation dielectric for liquid crystal on silicon structure and related method

#16 | 2006-07-18
US10850187
-

Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies

#17 | 2006-05-30
US10411054
-

Deep N wells in triple well structures and method for fabricating same

#18 | 2006-05-09
US10712067
-

Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies

#19 | 2005-09-13
US10073751
-

Method for fabricating a metal resistor in an IC chip and related structure

InventorID:

223299 ⎘