Yannick LE TIEC

Method for manufacturing a fin MOS transistor

Low leakage dual STI integrated circuit including FDSOI transistors

Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same

Method for fabricating microelectronic devices with isolation trenches partially formed under active regions

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Defective P-N junction for backgated fully depleted silicon on insulator mosfet

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Defective P-N junction for backgated fully depleted silicon on insulator MOSFET

Method for manufacturing a fin MOS transistor

Method for producing a field effect transistor with a SiGe channel by ion implantation

Method for producing a field effect transistor with implantation through the spacers

Microelectronic device with isolation trenches extending under an active area

Method for making a semiconductor structure with a buried ground plane

Method for treating the surface of a silicon substrate

Method of producing insulation trenches in a semiconductor on insulator substrate

Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same

Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer

Field effect transistor with offset counter-electrode contact

Method for fabricating a field effect device with weak junction capacitance

Field effect device provided with a localized dopant diffusion barrier area and fabrication method

Process for assembling substrates with low-temperature heat treatments

Method for making a semiconductor structure with a buried ground plane

PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS