Inventor profile of:

Harry Barowski

City:

Schoenaich

Country:

Germany

Published Applications:

15

Last publication date:

2026-06-18

Top Assignees for applications by Harry Barowski

The entities that hold a legal rights for patent applications filed by inventor Barowski Harry:

Recent patent applications by Barowski Harry

Harry Barowski from Schoenaich, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-18
US20260169630A1
Physics

PERFORMING A READ OPERATION AND A CLEAR OPERATION IN A LATE SELECT ARRAY IN THE SAME CLOCK CYCLE

#2 | 2026-06-02
US18981959
Physics

Performing a read operation and a clear operation in a late select array in the same clock cycle

#3 | 2023-03-02
US20230060610A1
Electricity

True complement dynamic circuit and method for combining binary data

#4 | 2023-02-02
US20230034436A1
Physics

QUANTUM CIRCUIT ARRANGEMENT

#5 | 2022-01-13
US20220013166A1
Physics

Erasing a partition of an SRAM array with hardware support

#6 | 2020-09-03
US20200279593A1
Physics

RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption

#7 | 2020-06-18
US20200194060A1
Physics

Global bit line latch performance and power optimization

#8 | 2020-05-28
US20200167684A1
Physics

QUBIT TUNING BY MAGNETIC FIELDS IN SUPERCONDUCTORS

#9 | 2020-05-28
US20200167683A1
Physics

Qubit tuning by magnetic fields in superconductors

#10 | 2020-04-23
US20200127649A1
Electricity

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

#11 | 2019-09-26
US20190294739A1
Physics

Layout of large block synthesis blocks in integrated circuits

#12 | 2019-07-18
US20190220570A1
Physics

Integrated circuit design changes using through-silicon vias

#13 | 2019-02-28
US20190065636A1
Physics

Layout of large block synthesis blocks in integrated circuits

#14 | 2019-02-28
US20190065635A1
Physics

Layout of large block synthesis blocks in integrated circuits

#15 | 2018-07-26
US20180212595A1
Electricity

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

InventorID:

2254541 ⎘