Austin, Texas
United States
28
2025-01-23
The entities that hold a legal rights for patent applications filed by inventor PUSDESRIS Joseph Michael:
Joseph Michael PUSDESRIS from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Predicting a load value for a subsequent load operation
#2 | 2023-12-28Methods and apparatus for transferring data within hierarchical cache circuitry
#3 | 2023-12-28Control flow prediction using pointers
#4 | 2023-09-21Operation elimination
#5 | 2023-07-20Producer prefetch filter
#6 | 2023-06-08Faulting address prediction for prefetch target address
#7 | 2023-04-20Responding to branch misprediction for predicated-loop-terminating branch instruction
#8 | 2023-04-13Prefetching
#9 | 2022-07-28PREDICTION CIRCUITRY
#10 | 2022-05-19REGISTER RENAME STAGE FUSING OF INSTRUCTIONS
#11 | 2022-05-12Data processing apparatus and method for generating prefetches
#12 | 2022-04-28Controlling access requests of request nodes
#13 | 2022-04-07Apparatus and method for controlling eviction from a storage structure
#14 | 2021-12-21Writebacks of prefetched data
#15 | 2021-11-30Apparatus and method for managing caches in a cache hierarchy
#16 | 2021-11-18Determining prefetch patterns with discontinuous strides
#17 | 2021-10-26Predicting an outcome of an instruction following a flush
#18 | 2021-09-02Shared pointer for local history records used by prediction circuitry
#19 | 2021-07-15Prefetching at dynamically determined offsets
#20 | 2021-02-25Cache eviction
#21 | 2020-06-04Cache retention data management
#22 | 2020-04-30Correlated addresses and prefetching
#23 | 2020-03-26Multiple stride prefetching
#24 | 2020-03-26Cache storage techniques
#25 | 2020-03-05Storage circuitry request tracking
#26 | 2019-11-14Memory controller having data access hint message for specifying the given range of one or more memory addresses
#27 | 2018-10-11Cache hierarchy management
#28 | 2018-08-09Memory controller having data access hint message for specifying the given range of one or more memory addresses
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