Douglas Michael REBER

CHIPS-ON-RAILS SYSTEM IN PACKAGE

SEMICONDUCTOR CIRCUIT WITH BACK-SIDE PARTIAL-SUBSTRATE POWER RAILS

SEMICONDUCTOR CIRCUIT WITH BACKSIDE PARTIAL SILICON VIAS USED FOR CONNECTIONS AND DECOUPLING CAPACITORS

INTERCONNECT STRUCTURE WITH RELAXED VIA-CORNER SLOPE

LOW-K INTERCONNECT DIELECTRIC BY SELECTIVE IMPLANTATION

ELECTRONIC DEVICES INCLUDING A SIDEWALL STRUCTURE AND METHODS OF FORMATION THEREOF

CIRCUIT FOR DETECTION AND MITIGATION OF DEVICE DAMAGE TO AN ELECTRONIC DEVICE

SEMICONDUCTOR CIRCUIT WITH SELECTIVE BACKSIDE POWER AND GROUND DISTRIBUTION AND MAXIMUM AREA DECOUPLING CAPACITORS

SEMICONDUCTOR DIE WITH BURIED ELECTRICAL INTERCONNECTIONS

LATCH-UP PREVENTION WITH WELL-TIE EXTENSION USING SELECTIVE WELL DOPING

METHOD FOR FORMING A REDUCED SIZE FEATURE

INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS

SEMICONDUCTOR WAFER FABRICATION WITH POLYIMIDE TO GRAPHENE CONVERSION

SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES

INTEGRATED CIRCUIT WITH OVERLAPPING STRESSORS

Plated pillar dies having integrated electromagnetic shield layers

Post contact air gap formation

Multigate transistor

Substrate contacts for a transistor