Cedric Lichtenau

ATOMIC SEQUENCES USING MULTIPLE CACHE LINES

TARGETED ACCELERATOR DISPATCH

CLASSIFYING AND SAMPLING EXECUTION EFFICIENCIES OF SOFTWARE LIBRARIES

TENSOR TRANSFORMATION

TENSOR PROCESSING FOR WITH MASKED ARTIFICIAL INTELLIGENCE FUNCTION BEHAVIOR

TENSOR PROCESSING WITH DIMENSION BROADCASTING

TENSOR MATRIX MULTIPLICATION WITH QUANTIZATION

DIMENSION CONTROL IN TENSOR MATRIX MULTIPLICATION

COHERENT COMMUNICATION BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

COHERENT COMMUNICATION BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

DECISION TREE TRAINING AND INFERENCE WITH MIXED PRECISION

PROCESSING TENSORS

Verifying the correctness of a leading zero counter

Rounding hexadecimal floating point numbers using binary incrementors

REDUCED LOGIC CONVERSION OF BINARY INTEGERS TO BINARY CODED DECIMALS

Variable replacement by an artificial intelligence accelerator

FLOATING-POINT CONVERSION WITH DENORMALIZATION

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

DYNAMIC ALGORITHM SELECTION

PADDING INPUT DATA FOR ARTIFICIAL INTELLIGENCE ACCELERATORS

Validating memory access patterns of static program code

ACCELERATING DECISION TREE INFERENCES BASED ON TENSOR OPERATIONS

OPERATING A SECURE CODE SEGMENT ON A PROCESSOR CORE OF A PROCESSING UNIT

ACCELERATING DECISION TREE INFERENCES BASED ON COMPLEMENTARY TENSOR OPERATION SETS

Scheduling a secure code segment on a processor core of a processing unit

Accelerator trustworthiness

PERFORMING A FLOATING-POINT MULTIPLY-ADD OPERATION IN A COMPUTER IMPLEMENTED ENVIRONMENT

Exception summary for invalid values detected during instruction execution

CONCATENATED INPUT/OUTPUT TENSORS FOR USE IN RECURRENT NEURAL NETWORKS

Single function to perform combined matrix multiplication and bias add operations

SINGLE FUNCTION TO PERFORM COMBINED CONVOLUTION AND SELECT OPERATIONS

RECURRENT NEURAL NETWORK CELL ACTIVATION TO PERFORM A PLURALITY OF OPERATIONS IN A SINGLE INVOCATION

REFORMATTING OF TENSORS TO PROVIDE SUB-TENSORS

Neural network processing assist instruction

Instruction to query for model-dependent information

Single function to perform multiple operations with distinct operation parameter validation

Vector convert hexadecimal floating point to scaled decimal instruction

Decimal scale and convert and split to hexadecimal floating point instruction

Data conversion to/from selected data type with implied rounding mode

Vector string search instruction

Reusing adjacent SIMD unit for fast wide result generation

Plausability-driven fault detection in result logic and condition codes for fast exact substring match

Plausibility-driven fault detection in string termination logic for fast exact substring match

Efficient checking of a condition code anticipator for a floating point processor and/or unit

Condition code anticipator for hexadecimal floating point

Instruction scheduling during execution in a processor

Fault-tolerant clock gating

Integrated circuit control latch protection

Vector string search instruction

Digit validation check control in instruction execution

LOAD/STORE BYTES REVERSED ELEMENTS INSTRUCTIONS

LOAD/STORE ELEMENTS REVERSED INSTRUCTIONS

Negative zero control in instruction execution

Instruction interrupt suppression of overflow exception

Method and apparatus for wiring multiple technology evaluation circuits

Non-overlapping substring detection within a data element string

Rapid substring detection within a data element string

Method and apparatus for processing storage instructions

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Computerized methods for prefetching data based on machine learned sequences of memory addresses

Rapid partial substring matching

Normalization of a product on a datapath

Method to build reconfigurable variable length comparators

Aligning most significant bits of different sized elements in comparison result vectors

Selection of variable memory-access size

Enhanced performance-aware instruction scheduling

Enhanced performance-aware instruction scheduling

Multiply-add operations of binary numbers in an arithmetic unit

Multiply-add operations of binary numbers in an arithmetic unit

Multiply-add operations of binary numbers in an arithmetic unit

Normalization of a product on a datapath

Normalization of a product on a datapath

ATE compatible high-efficient functional test

Rapid character substring searching

Computerized branch predictions and decisions

Computerized branch predictions and decisions

Checking a computer processor design for soft error handling

Checking a computer processor design for soft error handling

Combining of several execution units to compute a single wide scalar result

Decimal and binary floating point rounding

Identification of unknown sources for logic built-in self test in verification

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Bypassing an encoded latch on a chip during a test-pattern scan

Bypassing an encoded latch on a chip during a test-pattern scan

Binary fused multiply-add floating-point calculations

Binary fused multiply-add floating-point calculations

Reducing power requirements and switching during logic built-in-self-test and scan test

Reducing power requirements and switching during logic built-in-self-test and scan test

Reducing power requirements and switching during logic built-in-self-test and scan test

Reducing power requirements and switching during logic built-in-self-test and scan test

Decimal and binary floating point rounding

Identification of unknown sources for logic built-in self test in verification

Data access protection for computer systems

Data access protection for computer systems

Identification of unknown sources for logic built-in self test in verification

Checking arithmetic computations

Verification of intellectual property core trusted state

Verification of intellectual property core trusted state