Inventor profile of:

Guy G. Tracy

City:

Austin, Texas

Country:

United States

Published Applications:

16

Last publication date:

2026-06-09

Top Assignees for applications by Guy G. Tracy

The entities that hold a legal rights for patent applications filed by inventor Tracy Guy G.:

Recent patent applications by Tracy Guy G.

Guy G. Tracy from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-09
US18972834
Physics

Sub cache line position management

#2 | 2025-09-23
US18780623
Physics

Cache governance in a computing environment with multiple processors

#3 | 2023-10-10
US17808119
Physics

Preventing extraneous messages when exiting core recovery

#4 | 2023-10-05
US20230318979A1
Electricity

BIDIRECTIONAL RING-BASED INTERCONNECTION NETWORKS FOR MULTIPROCESSORS

#5 | 2020-10-15
US20200327058A1
Physics

Coherent cache with simultaneous data requests in same addressable index

#6 | 2019-11-28
US20190361783A1
Physics

Accuracy sensitive performance counters

#7 | 2019-08-15
US20190251037A1
Physics

NON-DISRUPTIVE CLEARING OF VARYING ADDRESS RANGES FROM CACHE

#8 | 2019-08-15
US20190251036A1
Physics

NON-DISRUPTIVE CLEARING OF VARYING ADDRESS RANGES FROM CACHE

#9 | 2019-06-13
US20190179765A1
Physics

Non-disruptive clearing of varying address ranges from cache

#10 | 2018-11-29
US20180341422A1
Physics

Operation interlocking in an address-sliced cache system

#11 | 2018-11-22
US20180336135A1
Physics

Ownership tracking updates across multiple simultaneous operations

#12 | 2018-11-22
US20180336134A1
Physics

Ownership tracking updates across multiple simultaneous operations

#13 | 2018-11-22
US20180336116A1
Physics

Accuracy sensitive performance counters

#14 | 2018-10-25
US20180307628A1
Physics

Deadlock avoidance in a multi-processor computer system with extended cache line locking

#15 | 2018-10-25
US20180307612A1
Physics

Non-disruptive clearing of varying address ranges from cache

#16 | 2018-08-21
US15716713
Physics

Non-disruptive clearing of varying address ranges from cache

InventorID:

2332325 ⎘