Inventor profile of:

Danilo Caraccio

City:

Milano

Country:

Italy

Published Applications:

88

Last publication date:

2026-04-02

Top Assignees for applications by Danilo Caraccio

The entities that hold a legal rights for patent applications filed by inventor Caraccio Danilo:

Recent patent applications by Caraccio Danilo

Danilo Caraccio from Milano, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-02
US20260093637A1
Physics

TRACKING ACCESSES TO A MEMORY USING A RING-BUFFER STRUCTURE

#2 | 2026-03-19
US20260080961A1
Physics

GLITCH DETECTION

#3 | 2026-02-12
US20260046144A1
Electricity

DEVICE IDENTIFIER COMPOSITION ENGINE 3-LAYER ARCHITECTURE

#4 | 2026-01-15
US20260018234A1
Physics

HOST CONTROLLED MEDIA TESTING OF MEMORY

#5 | 2025-12-18
US20250383968A1
Physics

MULTIPLE ACCESS TRACKERS FOR A MEMORY DEVICE

#6 | 2025-12-18
US20250383815A1
Physics

KEY IDENTIFIER CHECK IN A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE

#7 | 2025-12-11
US20250378864A1
Physics

FINITE TIME COUNTING PERIOD COUNTING OF INFINITE DATA STREAMS

#8 | 2025-12-11
US20250377793A1
Physics

ACCESS PATTERN TRACKING

#9 | 2025-11-06
US20250342031A1
Physics

FIELD FIRMWARE UPDATE

#10 | 2025-10-23
US20250328649A1
Physics

SECURE BOOT PROCEDURE

#11 | 2025-10-09
US20250315531A1
Physics

FIRMWARE AUTHENTICITY CHECK

#12 | 2025-10-02
US20250306766A1
Physics

MULTI-LEVEL ACCESS COUNTERS FOR A MEMORY DEVICE

#13 | 2025-09-25
US20250298694A1
Physics

USER DATA BLOCK LEVEL ACCESS COUNTER

#14 | 2025-09-18
US20250291507A1
Physics

MEMORY DEVICE ACCESS MONITORING UNIT INTERFACE

#15 | 2025-09-11
US20250284407A1
Physics

DYNAMIC ACCESS COUNTER THRESHOLD

#16 | 2025-07-31
US20250245098A1
Physics

ERROR MANAGEMENT OF MEMORY DEVICES

#17 | 2025-06-19
US20250199952A1
Physics

IN MEMORY COLD PAGES DETECTOR

#18 | 2025-06-05
US20250181448A1
Physics

MEMORY SCRUBBING BASED ON DETECTED CORRECTABLE ERROR

#19 | 2025-05-15
US20250156272A1
Physics

APPARATUS FOR REDUNDANT ARRAY OF INDEPENDENT DISKS

#20 | 2025-05-15
US20250156256A1
Physics

DETECTING PAGE FAULT TRAFFIC

#21 | 2025-05-08
US20250148133A1
Physics

SECURITY MANAGEMENT OF FERROELECTRIC MEMORY DEVICE

#22 | 2025-04-10
US20250117209A1
Physics

FIRMWARE VALIDATION FOR FIRMWARE UPDATES

#23 | 2025-03-20
US20250094344A1
Physics

CHAINED MAPPING WITH COMPRESSION

#24 | 2025-03-20
US20250094343A1
Physics

DYNAMIC PAGE MAPPING WITH COMPRESSION

#25 | 2025-03-20
US20250094278A1
Physics

RAS TRIGGERS L2P TABLE MOVEMENT IN CXL DEVICES WITH COMPRESSION

#26 | 2025-03-20
US20250094047A1
Physics

DUAL COMPRESSION IN MEMORY DEVICES

#27 | 2025-03-06
US20250077348A1
Physics

POST PACKAGE REPAIR RESOURCES FOR MEMORY DEVICES

#28 | 2025-02-27
US20250069680A1
Physics

POST PACKAGE REPAIR MANAGEMENT

#29 | 2025-02-13
US20250053343A1
Physics

ROW HAMMER TELEMETRY

#30 | 2025-02-13
US20250053222A1
Physics

PROVIDING ENERGY INFORMATION TO MEMORY

#31 | 2025-01-23
US20250028486A1
Physics

LOG MANAGEMENT MAINTENANCE OPERATION AND COMMAND

#32 | 2025-01-09
US20250013458A1
Physics

TECHNIQUES FOR MANAGING OFFLINE IDENTITY UPGRADES

#33 | 2024-12-12
US20240411466A1
Physics

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION

#34 | 2024-06-06
US20240185938A1
Physics

GLITCH DETECTION

#35 | 2024-03-21
US20240096439A1
Physics

SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE

#36 | 2024-03-21
US20240096438A1
Physics

ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A DRAM DEVICE

#37 | 2024-03-21
US20240095120A1
Physics

ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A CXL TYPE 3 DEVICE

#38 | 2024-03-14
US20240087664A1
Physics

Built-in self-test burst patterns based on architecture of memory

#39 | 2024-03-14
US20240087663A1
Physics

Built-in self-test circuitry

#40 | 2024-02-29
US20240070284A1
Physics

SECURE BOOT PROCEDURE

#41 | 2024-02-29
US20240070283A1
Physics

SECURE BOOT PROCEDURE

#42 | 2024-02-29
US20240069620A1
Physics

Providing energy information to memory

#43 | 2024-02-22
US20240061792A1
Physics

DATA IDENTITY RECOGNITION FOR SEMICONDUCTOR DEVICES

#44 | 2024-02-01
US20240036762A1
Physics

BLOOM FILTER INTEGRATION INTO A CONTROLLER

#45 | 2024-01-25
US20240028249A1
Physics

Controllers and methods for accessing memory devices via multiple modes

#46 | 2024-01-04
US20240007265A1
Electricity

DATA AUTHENTICITY AND INTEGRITY CHECK FOR DATA SECURITY SCHEMES

#47 | 2024-01-04
US20240004760A1
Physics

Apparatus for redundant array of independent disks

#48 | 2023-12-21
US20230409242A1
Physics

Storage traffic pattern detection in memory devices

#49 | 2023-12-07
US20230395184A1
Physics

Post package repair management

#50 | 2023-12-07
US20230393770A1
Physics

Memory device security and row hammer mitigation

#51 | 2023-11-16
US20230367663A1
Physics

Detecting page fault traffic

#52 | 2023-11-16
US20230367575A1
Physics

Techniques for managing offline identity upgrades

#53 | 2023-09-21
US20230297285A1
Physics

Row hammer telemetry

#54 | 2023-09-14
US20230290427A1
Physics

HOST CONTROLLED MEDIA TESTING OF MEMORY

#55 | 2023-09-14
US20230289270A1
Physics

HOST CONTROLLED ELECTRONIC DEVICE TESTING

#56 | 2023-09-07
US20230282258A1
Physics

Finite time counting period counting of infinite data streams

#57 | 2023-08-31
US20230274002A1
Physics

FIRMWARE AUTHENTICITY CHECK

#58 | 2023-03-30
US20230096375A1
Physics

Memory controller for managing data and error information

#59 | 2022-11-10
US20220357791A1
Physics

Providing energy information to memory

#60 | 2022-10-27
US20220342737A1
Physics

Detecting page fault traffic

#61 | 2022-10-20
US20220334773A1
Physics

Storage traffic pattern detection in memory devices

#62 | 2022-10-13
US20220326887A1
Physics

Log management maintenance operation and command

#63 | 2022-08-18
US20220261363A1
Physics

Controller for managing multiple types of memory

#64 | 2022-08-11
US20220253387A1
Physics

Memory tracing in an emulated computing system

#65 | 2022-06-30
US20220207193A1
Physics

Security management of ferroelectric memory device

#66 | 2022-02-17
US20220050734A1
Physics

Detecting page fault traffic

#67 | 2022-01-27
US20220027085A1
Physics

Storage traffic pattern detection in memory devices

#68 | 2021-12-30
US20210406411A1
Physics

Bus encryption for non-volatile memories

#69 | 2021-10-14
US20210319829A1
Physics

Dedicated commands for memory operations

#70 | 2021-06-24
US20210191887A1
Physics

Hybrid memory system interface

#71 | 2021-06-03
US20210166775A1
Physics

Data state synchronization

#72 | 2021-03-04
US20210064261A1
Physics

Multi-partitioning of memories

#73 | 2020-12-31
US20200409607A1
Physics

HYBRID MEMORY SYSTEM

#74 | 2020-11-05
US20200348999A1
Physics

Transaction metadata

#75 | 2020-09-24
US20200301841A1
Physics

Latency-based storage in a hybrid memory system

#76 | 2020-09-17
US20200293211A1
Physics

Latency-based storage in a hybrid memory system

#77 | 2020-07-09
US20200218645A1
Physics

Storage class memory status

#78 | 2020-03-12
US20200082900A1
Physics

Data state synchronization involving memory cells having an inverted data state written thereto

#79 | 2020-03-12
US20200082883A1
Physics

Dedicated commands for memory operations

#80 | 2020-03-12
US20200081853A1
Physics

Hybrid memory system interface

#81 | 2020-02-27
US20200064903A1
Physics

Providing energy information to memory

#82 | 2019-10-24
US20190324843A1
Physics

Transaction metadata

#83 | 2019-09-26
US20190294547A1
Physics

Latency-based storage in a hybrid memory system

#84 | 2019-09-26
US20190294363A1
Physics

Latency-based storage in a hybrid memory system

#85 | 2019-09-26
US20190294356A1
Physics

Latency-based storage in a hybrid memory system

#86 | 2019-08-29
US20190266078A1
Physics

Storage class memory status

#87 | 2019-06-06
US20190171385A1
Physics

Multi-partitioning of memories

#88 | 2018-11-22
US20180336146A1
Physics

Providing energy information to memory

InventorID:

2355572 ⎘