Rahul Mathur

CLOCKING SCHEME FOR MULTI-PORT REGISTER FILE

MEMORY POWER DIGITAL MULTIPLEXER

METHODS AND APPARATUS FOR WORKLOAD SCHEDULING

Buried Metal Techniques

CIRCUIT FOR MULTIPORT REGISTER FILE

INCREASED THROUGHPUT FOR READS IN STATIC RANDOM ACCESS MEMORY

INCREASED THROUGHPUT FOR WRITES TO MEMORY

Increased throughput for writes to memory

Power-Gate Structure

Multi-Transistor Bitcell Structure

Clock Circuitry for Memory Applications

Burst read with flexible burst length for on-chip memory

Buried Metal Techniques

METHODS AND APPARATUS FOR WORKLOAD SCHEDULING

Power-up header circuitry for multi-bank memory

Bitline Precharge Techniques

Buried Signal Wires for Memory Applications

TSV Coupled Integrated Circuits and Methods

Methods and circuits of spatial alignment

Multi-tier memory architecture

Circuitry apportioning of an integrated circuit

Multi-tier memory architecture

TSV coupled integrated circuits and methods

3D storage architecture with tier-specific controls

CAM device with 3D CAM cells

Read assist circuitry for memory applications

Selective clock adjustment during read and/or write memory operations

Circuitry for tracking bias voltage behavior

Redundancy circuitry for memory application

Read assist circuitry for memory applications

Level shifter with bypass

Clock generation circuitry for memory applications

Write assist circuitry

Retention voltages for integrated circuits