Hsinchu
Taiwan
47
2026-05-07
The entities that hold a legal rights for patent applications filed by inventor Cai Jin:
Jin Cai from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#2 | 2026-01-22SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF
#3 | 2025-12-04SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#4 | 2025-11-27TRANSISTOR WITH A NEGATIVE CAPACITANCE AND A METHOD OF CREATING THE SAME
#5 | 2025-11-20VERTICAL SELF ALIGNED GATE ALL AROUND TRANSISTOR
#6 | 2025-11-20DEVICE WITH GATE-TO-DRAIN VIA AND RELATED METHODS
#7 | 2025-10-02DIELECTRIC WALLS FOR COMPLEMENTARY FIELD EFFECT TRANSISTORS
#8 | 2025-09-252D CHANNEL WITH SELF-ALIGNED SOURCE/DRAIN
#9 | 2025-09-18SEMICONDUCTOR DEVICE HAVING A GATE CONTACT ON A LOW-K LINER
#10 | 2025-03-20FIELD EFFECT TRANSISTOR WITH DISABLED CHANNELS AND METHOD
#11 | 2024-12-26SEMICONDUCTOR STRUCTURE INCLUDING DIFFERENT DEVICES AND METHODS FOR MANUFACTURING THE SAME
#12 | 2024-11-14NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL
#13 | 2024-08-29Forming 3D Transistors Using 2D Van Der WAALS Materials
#14 | 2024-06-13VERTICAL SELF ALIGNED GATE ALL AROUND TRANSISTOR
#15 | 2024-04-11DEVICE WITH GATE-TO-DRAIN VIA AND RELATED METHODS
#16 | 2024-02-29Dielectric Walls for Complementary Field Effect Transistors
#17 | 2024-02-29SEMICONDUCTOR STRUCTURE WITH REDUCED PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME
#18 | 2023-11-30Ferroelectric Semiconductor Device and Method
#19 | 2023-11-30SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#20 | 2023-11-30Nano transistors with source/drain having side contacts to 2-D material
#21 | 2023-11-23FABRICATION METHOD OF A DOUBLE-GATE CARBON NANOTUBE TRANSISTOR
#22 | 2023-11-09CONTROL CIRCUIT, MEMORY SYSTEM AND CONTROL METHOD
#23 | 2023-10-19SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
#24 | 2023-10-12Memory array, memory structure and operation method of memory array
#25 | 2023-05-04Field effect transistor with disabled channels and method
#26 | 2023-02-09SEMICONDUCTOR DEVICE HAVING A GATE CONTACT ON A LOW-K LINER
#27 | 2023-02-092D CHANNEL WITH SELF-ALIGNED SOURCE/DRAIN
#28 | 2022-11-17Ferroelectric semiconductor device and method
#29 | 2022-11-17Memory device and method thereof
#30 | 2022-11-10Forming 3D transistors using 2D Van Der Waals materials
#31 | 2022-11-10Control circuit, memory system and control method
#32 | 2022-09-22Fabrication method of a double-gate carbon nanotube transistor
#33 | 2022-09-22TRANSISTOR WITH A NEGATIVE CAPACITANCE AND A METHOD OF CREATING THE SAME
#34 | 2022-08-112D-Channel Transistor Structure with Asymmetric Substrate Contacts
#35 | 2022-05-05Nano transistors with source/drain having side contacts to 2-D material
#36 | 2021-11-25Cryogenic integrated circuits
#37 | 2021-10-12Memory device and multi-level memory cell having ferroelectric storage element and magneto-resistive storage element
#38 | 2021-07-22Semiconductor device and manufacturing method thereof
#39 | 2021-06-17Forming 3D transistors using 2D van per waals materials
#40 | 2021-04-22Ferroelectric semiconductor device and method
#41 | 2021-03-04Memory device and method thereof
#42 | 2020-08-27Transistor with a negative capacitance and a method of creating the same
#43 | 2020-08-27Transistor with a negative capacitance and a method of creating the same
#44 | 2020-04-30Memory device and method thereof
#45 | 2020-04-23Transistor with a negative capacitance and a method of creating the same
#46 | 2018-12-06Structure for FinFET devices
#47 | 2018-12-06Method and structure for FinFET devices
2367489 ⎘