Austin, Texas
United States
47
2026-03-12
The entities that hold a legal rights for patent applications filed by inventor Powell Stephen J.:
Stephen J. Powell from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
CANCELLING UNUSED READ COMMANDS FOR ACCESSING DATA IN MEMORY
#2 | 2025-11-13DECODING AND EXECUTING MEMORY COMMAND WITH PARTIAL FRAME DATA
#3 | 2022-06-28Reduced system memory latency via a variable latency interface
#4 | 2021-07-15Refresh-hiding memory system staggered refresh
#5 | 2021-06-24Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#6 | 2021-04-15Speculative bank activate dynamic random access memory (DRAM) scheduler
#7 | 2021-02-11Speculative bank activate dynamic random access memory (DRAM) scheduler
#8 | 2020-04-09Information handling system with immediate scheduling of load operations
#9 | 2020-03-26Interface scheduler for a distributed memory system
#10 | 2020-03-05Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
#11 | 2020-02-06Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#12 | 2019-12-12DRAM bank activation management
#13 | 2019-08-15Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#14 | 2019-05-30Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
#15 | 2019-05-30Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#16 | 2019-05-30Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#17 | 2019-05-30Host controlled data chip address sequencing for a distributed memory buffer system
#18 | 2019-05-16DRAM bank activation management
#19 | 2019-04-25Memory request scheduling to improve bank group utilization
#20 | 2019-04-18Partial data replay in a distributed memory buffer system
#21 | 2018-09-18Partial data replay in a distributed memory buffer system
#22 | 2017-06-20Dynamically adjusting read data return sizes based on memory interface bus utilization
#23 | 2016-12-22Synchronization and order detection in a memory system
#24 | 2016-06-30Synchronization and order detection in a memory system
#25 | 2015-05-28Early data tag to allow data CRC bypass via a speculative memory data return protocol
#26 | 2015-05-28Early data tag to allow data CRC bypass via a speculative memory data return protocol
#27 | 2015-05-21DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK
#28 | 2015-05-21Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold
#29 | 2014-12-25Memory uncorrectable error handling technique for reducing the impact of noise
#30 | 2014-12-25Memory uncorrectable error handling technique for reducing the impact of noise
#31 | 2014-12-18Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler
#32 | 2014-12-18Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler
#33 | 2014-10-16Modification of prefetch depth based on high latency event
#34 | 2014-10-16Modification of prefetch depth based on high latency event
#35 | 2014-10-09Method and apparatus for mitigating effects of memory scrub operations on idle time power savings mode
#36 | 2014-10-09Method and apparatus for mitigating effects of memory scrub operations on idle time power savings modes
#37 | 2014-09-18Synchronization and order detection in a memory system
#38 | 2014-02-20MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH-LATENCY MEMORY OPERATIONS
#39 | 2013-08-15Memory reorder queue biasing preceding high latency operations
#40 | 2013-07-04Method for scheduling memory refresh operations including power states
#41 | 2013-06-13Weighted history allocation predictor algorithm in a hybrid cache
#42 | 2013-06-13Weighted history allocation predictor algorithm in a hybrid cache
#43 | 2013-06-13Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth
#44 | 2013-06-13Dynamic inclusive policy in a hybrid cache hierarchy using hit rate
#45 | 2013-05-30Apparatus for scheduling memory refresh operations including power states
#46 | 2013-05-09Memory queue handling techniques for reducing impact of high-latency memory operations
#47 | 2010-10-21Load request scheduling in a cache hierarchy
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