Eric E. Retter

Dynamically allocating memory controller resources for extended prefetching

Scalable data collection for system management

Remote node broadcast of requests in a multinode data processing system

Remote node broadcast of requests in a multinode data processing system

Dynamically adjusting read data return sizes based on interconnect bus utilization

Dynamically adjusting read data return sizes based on interconnect bus utilization

Dynamically adjusting read data return sizes based on memory interface bus utilization

Synchronization and order detection in a memory system

Synchronization and order detection in a memory system

Scalable data collection for system management

ECC bypass using low latency CE correction with retry select signal

ECC bypass using low latency CE correction with retry select signal

Performing arithmetic operations using both large and small floating point values

Dual asynchronous and synchronous memory system

Dynamic reservations in a unified request queue

Dynamic reservations in a unified request queue

Modification of prefetch depth based on high latency event

Modification of prefetch depth based on high latency event

Provision of early data from a lower level cache memory

Provision of early data from a lower level cache memory

Transient condition management utilizing a posted error detection processing protocol

Transient condition management utilizing a posted error detection processing protocol

Dual asynchronous and synchronous memory system

Synchronization and order detection in a memory system

Tagging in memory control unit (MCU)

Address mapping including generic bits for universal addressing independent of memory type

Scalable data collection for system management

Selective posted data error detection based on history

Selective posted data error detection based on history

Memory reorder queue biasing preceding high latency operations

MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH-LATENCY MEMORY OPERATIONS

Memory reorder queue biasing preceding high latency operations

Synchronized command throttling for multi-channel duty-cycle based memory power management

Performing arithmetic operations using both large and small floating point values

Performing arithmetic operations using both large and small floating point values

Memory queue handling techniques for reducing impact of high-latency memory operations

Computer system and method of protection for the system's marking store

Implementing enhanced memory reliability using memory scrub operations

System to improve miscorrection rates in error control code through buffering and associated methods

System to improve error correction using variable latency and associated methods

System to improve memory failure management and associated methods

System for error decoding with retries and associated methods

Power-on initialization and test for a cascade interconnect memory system

Access speculation predictor with predictions based on memory region prior requestor tag information

Access speculation predictor with predictions based on a scope predictor

Access speculation predictor with predictions based on a domain indicator of a cache line

Access speculation predictor implemented via idle command processing resources

Methods, systems, and computer program products for dynamic selective memory mirroring

Switching a defective signal line with a spare signal line without shutting down the computer system

Memory wrap test mode using functional read/write buffers

Systems and methods for memory module power management

Switching a defective signal line with a spare signal line without shutting down the computer system

Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction

Real time clock circuit having an internal clock generator

Real time clock circuit having an internal clock generator