Markham
Canada
89
2024-12-05
The entities that hold a legal rights for patent applications filed by inventor Mitran Marcel:
Marcel Mitran from Markham, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
CONFIDENTIAL GRID COMPUTING
#2 | 2019-11-07Conditional instruction end operation
#3 | 2019-10-24Identifying processor attributes based on detecting a guarded storage event
#4 | 2019-10-17Conditional transaction end instruction
#5 | 2019-06-20Transactional lock elision with delayed lock checking
#6 | 2019-04-18Transaction begin/end instructions
#7 | 2019-02-14Compare and delay instructions
#8 | 2018-10-18Conditional transaction end instruction
#9 | 2018-07-19Load logical and shift guarded instruction
#10 | 2018-07-19Identifying processor attributes based on detecting a guarded storage event
#11 | 2018-07-19Loading and storing controls regulating the operation of a guarded storage facility
#12 | 2017-05-18Conditional instruction end operation
#13 | 2017-05-11Conditional instruction end operation
#14 | 2017-04-27DYNAMIC DETERMINATION OF THE APPLICABILITY OF A HARDWARE ACCELERATOR TO A REQUEST
#15 | 2017-04-27DYNAMIC DETERMINATION OF THE APPLICABILITY OF A HARDWARE ACCELERATOR TO A REQUEST
#16 | 2016-12-22Transactional lock elision with delayed lock checking
#17 | 2016-12-01Transaction abort instruction specifying a reason for abort
#18 | 2016-12-01Transaction abort instruction specifying a reason for abort
#19 | 2016-11-24Conditional transaction end instruction
#20 | 2016-09-15Transaction begin/end instructions
#21 | 2016-07-21Convert to zoned format from decimal floating point format
#22 | 2016-07-21Convert from zoned format to decimal floating point format
#23 | 2016-07-21Convert from zoned format to decimal floating point format
#24 | 2016-07-21Convert to zoned format from decimal floating point format
#25 | 2016-07-14Computer system using partially functional processor core
#26 | 2016-03-31MACHINE INSTRUCTIONS FOR CONVERTING FROM DECIMAL FLOATING POINT FORMAT TO PACKED DECIMAL FORMAT
#27 | 2016-03-31MACHINE INSTRUCTIONS FOR CONVERTING TO DECIMAL FLOATING POINT FORMAT FROM PACKED DECIMAL FORMAT
#28 | 2016-03-31MACHINE INSTRUCTIONS FOR CONVERTING FROM DECIMAL FLOATING POINT FORMAT TO PACKED DECIMAL FORMAT
#29 | 2016-03-31MACHINE INSTRUCTIONS FOR CONVERTING TO DECIMAL FLOATING POINT FORMAT FROM PACKED DECIMAL FORMAT
#30 | 2016-02-23Efficient code cache management in presence of infrequently used complied code fragments
#31 | 2015-09-17Conditional instruction end operation
#32 | 2015-09-17Conditional instruction end operation
#33 | 2015-09-17Conditional transaction end instruction
#34 | 2015-09-17Conditional transaction end instruction
#35 | 2015-09-17Compare and delay instructions
#36 | 2015-09-17Compare and delay instructions
#37 | 2015-04-30Safe conditional-load and conditional-store operations
#38 | 2015-03-26Convert to zoned format from decimal floating point format
#39 | 2015-03-26Convert from zoned format to decimal floating point format
#40 | 2014-10-02Transactional lock elision with delayed lock checking
#41 | 2014-10-02Transactional lock elision with delayed lock checking
#42 | 2013-12-19Transaction begin/end instructions
#43 | 2013-12-19Transaction diagnostic block
#44 | 2013-12-19Transaction diagnostic block
#45 | 2013-12-19Transaction abort instruction
#46 | 2013-12-19Program interruption filtering in transactional execution
#47 | 2013-12-19Program interruption filtering in transactional execution
#48 | 2013-12-19Branch prediction preloading
#49 | 2013-12-19Branch prediction preloading
#50 | 2013-12-19Transaction abort instruction
#51 | 2013-12-19Transaction begin/end instructions
#52 | 2013-09-19Controlling operation of a run-time instrumentation facility from a lesser-privileged state
#53 | 2013-09-19Hardware based run-time instrumentation facility for managed run-times
#54 | 2013-09-19Hardware based run-time instrumentation facility for managed run-times
#55 | 2013-09-19Run-time instrumentation monitoring of processor characteristics
#56 | 2013-09-19Controlling operation of a run-time instrumentation facility
#57 | 2013-09-19Run-time instrumentation reporting
#58 | 2013-09-19Run-time-instrumentation controls emit instruction
#59 | 2013-09-19Run-time instrumentation directed sampling
#60 | 2013-09-19Run-time-instrumentation controls emit instruction
#61 | 2013-09-05Self initialized host cell spatially aware emulation of a computer instruction set
#62 | 2013-07-04Convert to zoned format from decimal floating point format
#63 | 2013-07-04Convert from zoned format to decimal floating point format
#64 | 2013-05-09Load pair disjoint facility and instruction therefor
#65 | 2013-05-09High-word facility for extending the number of general purpose registers available to instructions
#66 | 2012-08-02Mining sequential patterns in weighted directed graphs
#67 | 2012-06-28Batch dispatch of java native interface calls
#68 | 2012-05-10PROGRAMMATIC DISPATCH TO FUNCTIONS WITH MATCHING LINKAGE
#69 | 2011-08-18Load pair disjoint facility and instruction therefore
#70 | 2011-08-18Executing atomic store disjoint instructions
#71 | 2011-05-05Eliminating redundant operations for common properties using shared real registers
#72 | 2011-03-24Just in time compiler in spatially aware emulation of a guest computer instruction set
#73 | 2011-03-24Host cell spatially aware emulation of a guest wild branch
#74 | 2011-03-24Self initialized host cell spatially aware emulation of a computer instruction set
#75 | 2011-03-24Page mapped spatially aware emulation of a computer instruction set
#76 | 2010-09-30Mining sequential patterns in weighted directed graphs
#77 | 2010-07-29Providing code improvements for nested virtual machines
#78 | 2010-04-22Exploiting Register High-Words
#79 | 2009-10-15Defining memory indifferent trace handles
#80 | 2009-07-30Performance improvements for nested virtual machines
#81 | 2009-05-21Cache line reservations
#82 | 2009-05-07METHODS AND COMPUTER PROGRAM PRODUCTS FOR IMPLEMENTING LOW-COST POINTER COMPRESSION AND DECOMPRESSION
#83 | 2009-03-05Methods, systems, and computer products for evaluating robustness of a list scheduling framework
#84 | 2009-02-26METHODS AND COMPUTER PROGRAM PRODUCTS FOR REDUCING LOAD-HIT-STORE DELAYS BY ASSIGNING MEMORY FETCH UNITS TO CANDIDATE VARIABLES
#85 | 2008-10-02Controlling tracing within compiled code
#86 | 2008-09-04Configuring a dependency graph for dynamic by-pass instruction scheduling
#87 | 2008-07-24Defining memory indifferent trace handles
#88 | 2008-07-10Automatic inspection of compiled code
#89 | 2008-04-24Method, computer program product, and device for selectively allocating memory
238922 ⎘