Inventor profile of:

SHIANG-BAU WANG

City:

Pingzchen

Country:

Taiwan

Published Applications:

62

Last publication date:

2024-09-05

Top Assignees for applications by SHIANG-BAU WANG

The entities that hold a legal rights for patent applications filed by inventor WANG SHIANG-BAU:

Recent patent applications by WANG SHIANG-BAU

SHIANG-BAU WANG from Pingzchen, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-09-05
US20240297225A1
Electricity

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

#2 | 2024-04-18
US20240128126A1
Electricity

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVCE

#3 | 2023-11-23
US20230377990A1
Electricity

SEMICONDUCTOR DEVICE AND METHOD

#4 | 2023-10-26
US20230343853A1
Electricity

Partial directional etch method and resulting structures

#5 | 2023-08-10
US20230253479A1
Electricity

Air spacer and method of forming same

#6 | 2023-04-13
US20230113320A1
Electricity

Semiconductor device and method

#7 | 2023-03-02
US20230060763A1
Electricity

Method of manufacturing a semiconductor device and a semiconductor device

#8 | 2022-10-13
US20220328656A1
Electricity

Partial directional etch method and resulting structures

#9 | 2022-09-08
US20220285530A1
Electricity

Air spacer and method of forming same

#10 | 2022-08-18
US20220262920A1
Electricity

Semiconductor device and method of manufacture

#11 | 2022-02-24
US20220059685A1
Electricity

Cut-fin isolation regions and method forming same

#12 | 2021-12-30
US20210408266A1
Electricity

Air spacer and method of forming same

#13 | 2021-11-11
US20210351084A1
Electricity

Semiconductor device and method

#14 | 2021-08-26
US20210265487A1
Electricity

Partial directional etch method and resulting structures

#15 | 2021-08-05
US20210242192A1
Electricity

Metal gate structure cutting process

#16 | 2021-07-22
US20210226033A1
Electricity

Semiconductor device and method of manufacture

#17 | 2021-03-25
US20210090958A1
Electricity

Method of manufacturing a semiconductor device

#18 | 2021-03-11
US20210074579A1
Electricity

Semiconductor device and method

#19 | 2020-11-19
US20200364844A1
Physics

Semiconductor wafer measurement method and system

#20 | 2020-06-04
US20200176318A1
Electricity

Method of manufacturing a semiconductor device

#21 | 2020-04-23
US20200126868A1
Electricity

Semiconductor device and method

#22 | 2020-04-02
US20200105583A1
Electricity

Semiconductor device and method

#23 | 2020-02-06
US20200044070A1
Electricity

Cut-fin isolation regions and method forming same

#24 | 2020-01-02
US20200004134A1
Physics

Lithography mask and method

#25 | 2019-08-22
US20190259140A1
Physics

Semiconductor wafer measurement method and system

#26 | 2019-05-02
US20190131122A1
Electricity

Semiconductor structure with etched fin structure

#27 | 2019-04-11
US20190109126A1
Electricity

Metal gate structure cutting process

#28 | 2019-01-03
US20190006345A1
Electricity

Metal gate structure cutting process

#29 | 2019-01-03
US20190004416A1
Physics

Lithography mask and method

#30 | 2017-09-07
US20170256390A1
Electricity

Semiconductor structure with etched fin structure

#31 | 2017-03-30
US20170092548A1
Electricity

Intelligent metrology based on module knowledge

#32 | 2017-02-02
US20170033105A1
Electricity

Method of forming metal gate to mitigate antenna defect

#33 | 2016-06-23
US20160181360A1
Electricity

Method for forming semiconductor structure with etched fin structure

#34 | 2016-03-03
US20160064377A1
Electricity

Fin field effect transistor (FinFET) device with protection layer

#35 | 2015-12-31
US20150380209A1
Electricity

Dimension measurement apparatus calibration standard and method for forming the same

#36 | 2015-12-17
US20150364559A1
Electricity

Integrated circuit having a contact etch stop layer

#37 | 2014-06-19
US20140170846A1
Electricity

Sidewall-free CESL for enlarging ILD gap-fill window

#38 | 2014-03-13
US20140073097A1
Electricity

Method of dual EPI process for semiconductor device

#39 | 2014-03-13
US20140073096A1
Electricity

Method of dual epi process for semiconductor device

#40 | 2014-02-27
US20140057409A1
Electricity

Isolation structure profile for gap filing

#41 | 2014-02-27
US20140054744A1
Electricity

Isolation structure profile for gap filing

#42 | 2014-01-09
US20140011348A1
Electricity

Wafer alignment system and method

#43 | 2013-12-19
US20130337631A1
Chemistry; metallurgy

Semiconductor structure and method

#44 | 2013-10-17
US20130270651A1
Electricity

Sidewall free CESL for enlarging ILD gap-fill window

#45 | 2013-08-01
US20130193519A1
Electricity

End-to-end gap fill using dielectric film

#46 | 2013-05-23
US20130130461A1
Electricity

Process for forming a metal oxide semiconductor devices

#47 | 2013-05-23
US20130126982A1
Electricity

Epitaxial process for forming semiconductor devices

#48 | 2013-05-16
US20130122699A1
Electricity

Hard mask removal method

#49 | 2013-01-17
US20130015533A1
Electricity

Epitaxial process for forming semiconductor devices

#50 | 2012-08-30
US20120217587A1
Electricity

Post CMP planarization by cluster ion beam etch

#51 | 2012-08-16
US20120205774A1
Electricity

Isolation structure profile for gap filling

#52 | 2012-08-16
US20120205746A1
Electricity

End-to-end gap fill using dielectric film

#53 | 2012-04-26
US20120098070A1
Electricity

Integrated circuit having a contact etch stop layer and method of forming the same

#54 | 2012-01-05
US20120003806A1
Electricity

Method of fabricating integrated circuit device, including removing at least a portion of a spacer

#55 | 2011-12-22
US20110312180A1
Electricity

Post CMP planarization by cluster ION beam etch

#56 | 2011-09-22
US20110230029A1
Electricity

Method of fabricating gate electrode using a hard mask with spacers

#57 | 2011-08-18
US20110201164A1
Electricity

Method of dual EPI process for semiconductor device

#58 | 2011-08-11
US20110195575A1
Electricity

Hard mask removal method

#59 | 2011-08-11
US20110195548A1
Electricity

Method of fabricating gate electrode using a treated hard mask

#60 | 2011-07-14
US20110171804A1
Electricity

Multilayer hard mask

#61 | 2011-05-24
US12892331
-

Method of forming a shallow trench isolation structure

#62 | 2011-01-13
US20110006390A1
Electricity

STI structure and method of forming bottom void in same

InventorID:

2394372 ⎘