Hsinchu
Taiwan
102
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor Chen Chung-Hui:
Chung-Hui Chen from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
HYBRID DECOUPLING CAPACITOR AND METHOD FORMING SAME
#2 | 2025-11-06THREE-DIMENSIONAL INTEGRATED CIRCUITS AND METHODS OF FORMING
#3 | 2025-10-30Package with Integrated Voltage Regulator and Method Forming the Same
#4 | 2025-10-30INTEGRATED CIRCUIT DEVICE LAYOUT, SYSTEM AND METHOD
#5 | 2025-08-14INTEGRATED CIRCUIT DEVICE AND METHOD
#6 | 2025-06-26THREE-DIMENSIONAL INTEGRATED CIRCUITS AND METHODS OF FORMING
#7 | 2025-03-27SEMICONDUCTOR DEVICES INCLUDING DECOUPLING CAPACITORS
#8 | 2024-11-28SEMICONDUCTOR DEVICE HAVING ARTIFACT STRUCTURES AND METHOD OF FABRICATITNG THE SAME
#9 | 2024-11-28SEMICONDUCTOR DEVICE, AND METHOD OF FORMING SAME
#10 | 2024-11-21CAPACITOR IN NANOSHEET
#11 | 2024-10-31INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT LAYOUT
#12 | 2024-10-03INTEGRATED CIRCUIT DEVICE
#13 | 2024-07-11SILICIDE-LAYER-COUPLED DOPED PORTION OF ACTIVE REGION AND METHOD OF FABRICATING SAME
#14 | 2024-03-21Semiconductor device and method
#15 | 2024-02-15PACKAGE WITH INTEGRATED VOLTAGE REGULATOR AND METHOD FORMING THE SAME
#16 | 2023-11-30Semiconductor devices including decoupling capacitors
#17 | 2023-08-31Integrated circuit device
#18 | 2023-06-01Zero mask high density capacitor
#19 | 2023-05-18Silicide-sandwiched source/drain region and method of fabricating same
#20 | 2023-05-18CELL HAVING STACKED PICK-UP REGION
#21 | 2023-03-02Semiconductor device, and method of forming same
#22 | 2022-12-22Standard cell design
#23 | 2022-11-17Cell placement optimization
#24 | 2022-11-10Semiconductor devices including decoupling capacitors
#25 | 2022-11-10Cell having stacked pick-up region
#26 | 2022-11-03THERMOELECTRIC STRUCTURE AND MANUFACTURING METHOD
#27 | 2022-10-06Semiconductor device structure with resistive element
#28 | 2022-09-22Capacitor and method for forming the same
#29 | 2022-09-01CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND DESIGN RULES
#30 | 2022-09-01Capacitor in nanosheet
#31 | 2022-09-01Semiconductor device and method of manufacturing the same
#32 | 2022-09-01CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND FIN BOUNDARIES
#33 | 2022-06-30Hybrid Decoupling Capacitor and Method Forming Same
#34 | 2021-12-23THERMOELECTRIC STRUCTURE AND METHOD
#35 | 2021-12-16Method of manufacturing conductive lines in a circuit
#36 | 2021-12-02Silicide-sandwiched source/drain region and method of fabricating same
#37 | 2021-12-02Integrated circuit device, system and method
#38 | 2021-12-02METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING DIFFERENT ARCHITECTURES AND SEMICONDUCTOR DEVICES FABRICATED THEREBY
#39 | 2021-11-18Integrated circuit device having active region coupled to metal layers on opposite sides of substrate, and method
#40 | 2021-11-18Semiconductor device and method
#41 | 2021-11-18Semiconductor devices including decoupling capacitors
#42 | 2021-07-29Method for forming decoupling capacitors between the interposing conductors and the multiple gates
#43 | 2020-11-26Zero mask high density capacitor
#44 | 2020-07-30Semiconductor device, method of generating layout diagram and system for same
#45 | 2020-04-23Decoupling capacitor
#46 | 2020-04-23Cell having stacked pick-up region
#47 | 2020-04-16Hybrid decoupling capacitor and method forming same
#48 | 2020-02-20Semiconductor structure
#49 | 2019-12-19Decoupling FinFET capacitors
#50 | 2019-11-07Methods and apparatus for MOS capacitors in replacement gate process
#51 | 2019-11-07Method of manufacturing conductive lines in a circuit
#52 | 2019-09-12Semiconductor device structure with resistive element
#53 | 2019-08-22Circuits using gate-all-around technology
#54 | 2019-01-31Decoupling capacitor
#55 | 2019-01-03Hybrid decoupling capacitor and method forming same
#56 | 2018-11-22Semiconductor device structure with resistive element
#57 | 2018-06-28Circuits using gate-all-around technology
#58 | 2018-05-31Semiconductor device and layout method
#59 | 2018-01-11Method of forming conductive lines in circuits
#60 | 2017-11-30Decoupling capacitor
#61 | 2017-10-19Thermal sensor
#62 | 2017-08-31Decoupling capacitor
#63 | 2017-07-20Circuits using gate-all-around technology
#64 | 2017-06-22Bandgap reference circuit
#65 | 2017-04-13Decoupling finFET capacitors
#66 | 2017-03-23Semiconductor device with self-heat reducing layers
#67 | 2016-06-16Circuits using gate-all-around technology
#68 | 2015-12-10Generating a semiconductor component layout
#69 | 2015-11-19Decoupling capacitor and method of making same
#70 | 2015-11-19Conductive lines in circuits
#71 | 2015-10-22Circuits using gate-all-around technology
#72 | 2015-07-16Semiconductor device with self-heat reducing layers
#73 | 2015-04-30MOS-based voltage reference circuit
#74 | 2015-01-01Generating a semiconductor component layout
#75 | 2014-12-18Thermal sensor
#76 | 2014-12-18Temperature/voltage detection circuit
#77 | 2014-11-06Integrated circuit having shielding structure
#78 | 2014-08-28Guard structure for semiconductor structure and method of forming guard layout pattern for semiconductor layout pattern
#79 | 2014-06-12Decoupling capacitor and method of making same
#80 | 2014-03-20Diode structures using fin field effect transistor processing and method of forming the same
#81 | 2014-03-20Device layout for reference and sensor circuits
#82 | 2014-01-09Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
#83 | 2013-12-26Semiconductor device feature density gradient verification
#84 | 2013-12-12Device layout for reference and sensor circuits
#85 | 2013-12-12Homo-junction diode structures using fin field effect transistor processing
#86 | 2013-11-21Bandgap reference circuit
#87 | 2013-08-08FinFET structure with novel edge fins
#88 | 2013-08-01Semiconductor device feature density gradient verification
#89 | 2013-08-01Decoupling finFET capacitors
#90 | 2013-08-01Decoupling capacitor and layout for the capacitor
#91 | 2013-07-18Method of and system for generating optimized semiconductor component layout
#92 | 2013-07-18Decoupling capacitor and method of making same
#93 | 2013-07-11Decoupling capacitor and method of making same
#94 | 2013-07-04Level shifting circuit and semiconductor device using the same
#95 | 2013-06-27Integrated circuits with reduced voltage across gate dielectric and operating methods thereof
#96 | 2013-06-13Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
#97 | 2013-02-21Low power/high speed TSV interface design
#98 | 2012-05-03Integrated circuits and fabrication methods thereof
#99 | 2012-04-19Integrated circuits with reduced voltage across gate dielectric and operating methods thereof
#100 | 2007-07-12Apparatus for detecting a current and temperature for an integrated circuit
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