Jan-Peter SCHAT

SCAN FLIP-FLOP

TEST SYSTEM FOR DETECTING FAULTS IN MULTIPLE DEVICES OF THE SAME TYPE

Securing cryptographic operations from side channel attacks using a chaotic oscillator

Secure key generation using a chaotic oscillator

Testing a memory which includes conservative reversible logic

Feedback system monitoring

Apparatus to cryptographically provide a digital output signal as a response to a challenge

PLL jitter detection

Communications system

Memory testing

System and method for obfuscating opcode commands in a semiconductor device

Detection of a cold boot memory attack in a data processing system

High data rate transmission using minimum energy coding with ultra wide band modulation

Logic and flip-flop circuit timing margins controlled based on scan-pattern transition processing

System and method for generating and authenticating a physically unclonable function

System and method for performing netlist obfuscation for a semiconductor device

Method and apparatus comprising a semiconductor device and test apparatus

Test apparatus and method for testing a semiconductor device

Vehicle access based on RF digests/backgrounds

Wireless communication device and method for spying counter measures

Method and system for detecting an attack on a physically unclonable function (PUF)

Combined ECC and transparent memory test for memory fault detection

System and method for triggering and detecting hardware trojans

Integrated circuit device die with wafer/package detection circuit

Apparatuses involving calibration of input offset voltage and signal delay of circuits and methods thereof

Non-intrusive fault detection for phase-locked loop

Methods for detecting system-level trojans and an integrated circuit device with system-level trojan detection

Apparatuses and methods involving a circuit for detecting a hardware-trojan

Apparatuses and methods involving authentication of radar-based digital data stream using cryptographic hashing

Data transmission code and interface

Internally clocked logic built-in self-test apparatuses and methods

Data transmission code and interface

Enabling secure internet transactions in an unsecure home using immobile token

Test system with embedded tester

Voltage regulator error detection and correction

Self-test apparatuses having distributed self-test controller circuits and controller circuitry to control self-test execution based on self-test properties and method thereof

Apparatuses and methods involving error detection and correction of linear analog circuits

Integrated circuit device with integrated fault monitoring system

Analog-test-bus apparatuses involving calibration of comparator circuits and methods thereof

Wired-data bus transmission using signal transition coding

APPARATUSES HAVING DIVERSIFIED LOGIC CIRCUITS AND METHODS THEREOF

Apparatuses and methods involving adjustable circuit-stress test conditions for stressing regional circuits

Wireless receiver and method for detecting an attack on a keyless entry system for a vehicle

METHODS AND APPARATUSES INVOLVING VEHICLE TOW-AWAY DETECTION

Method for protecting a passive keyless entry system against a relay attack

Apparatuses and methods involving self-testing voltage regulation circuits

Intrusion detection for integrated circuits

Monitor system for detecting defeat devices in engine control units

Method for triggering and detecting a malicious circuit in an integrated circuit device

Method and device for detecting a malicious circuit on an integrated circuit

Self-testing of an analog mixed-signal circuit using pseudo-random noise

Self-testing of a phase-locked loop using a pseudo-random noise

Built-in self-test for a radar unit receiver and method therefor

Apparatus for prediction of failure of a functional circuit

Built-in self-test radar unit and method for phase shift measurement therein

RF radar device BIST using noise injection

Integrated circuit fault detection

RF radar device BIST using secondary modulation