Campbell, California
United States
54
2020-09-17
The entities that hold a legal rights for patent applications filed by inventor Lambert Carole:
Carole Lambert from Campbell, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
#2 | 2018-06-21Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
#3 | 2017-12-21Optimizing Layout of Irregular Structures in Regular Layout Context
#4 | 2017-06-15Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
#5 | 2017-04-06Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
#6 | 2016-03-17Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
#7 | 2016-03-17Enforcement of semiconductor structure regularity for localized transistors and interconnect
#8 | 2015-07-02Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
#9 | 2014-12-18Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
#10 | 2014-10-02Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
#11 | 2014-08-28Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
#12 | 2014-07-31Integrated circuit within semiconductor chip including cross-coupled transistor configuration
#13 | 2014-07-17Enforcement of semiconductor structure regularity for localized transistors and interconnect
#14 | 2013-10-03Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
#15 | 2013-09-26Enforcement of semiconductor structure regularity for localized transistors and interconnect
#16 | 2013-08-22Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
#17 | 2013-08-15Finfet transistor circuit
#18 | 2013-08-15Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
#19 | 2013-08-15Cross-coupled transistor circuit including offset inner gate contacts
#20 | 2013-08-15Cross-coupled transistor circuit defined on four gate electrode tracks
#21 | 2013-08-08Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
#22 | 2013-08-08Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
#23 | 2013-08-08Cross-coupled transistor circuit defined on three gate electrode tracks
#24 | 2013-08-08Cross-coupled transistor circuit defined on two gate electrode tracks
#25 | 2013-08-01Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
#26 | 2013-06-13Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
#27 | 2013-05-23Circuits with linear finfet structures
#28 | 2013-05-16Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
#29 | 2012-12-06Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
#30 | 2010-10-14Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
#31 | 2010-10-07Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
#32 | 2010-10-07Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel
#33 | 2010-10-07Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
#34 | 2010-10-07Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region
#35 | 2010-09-23Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
#36 | 2010-09-23Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature
#37 | 2010-09-23Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode
#38 | 2010-09-23Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact
#39 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
#40 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
#41 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts
#42 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
#43 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications
#44 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
#45 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
#46 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships
#47 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
#48 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
#49 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
#50 | 2010-07-29Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer
#51 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
#52 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
#53 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
#54 | 2010-07-29Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
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