Inventor profile of:

Nelson Wu

City:

Austin, Texas

Country:

United States

Published Applications:

16

Last publication date:

2026-01-15

Top Assignees for applications by Nelson Wu

The entities that hold a legal rights for patent applications filed by inventor Wu Nelson:

Recent patent applications by Wu Nelson

Nelson Wu from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-15
US20260017160A1
Physics

MICROPROCESSOR VALIDATION USING RANDOM PREPACKAGED GENERATED TEST FUNCTIONS AND USER LEVEL SCHEDULER

#2 | 2024-01-25
US20240028518A1
Physics

Performance and reliability of processor store operation data transfers

#3 | 2023-06-22
US20230195981A1
Physics

HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR

#4 | 2023-06-22
US20230195649A1
Physics

Validation of store coherence relative to page translation invalidation

#5 | 2023-04-20
US20230122466A1
Physics

Cache coherence validation using delayed fulfillment of L2 requests

#6 | 2023-04-06
US20230105945A1
Physics

Validation of store coherence relative to page translation invalidation

#7 | 2021-09-30
US20210303766A1
Physics

Pre-silicon chip model of extracted workload inner loop instruction traces

#8 | 2020-03-19
US20200089621A1
Physics

Method, system, and apparatus for stress testing memory translation tables

#9 | 2020-01-30
US20200035319A1
Physics

System and method for testing processor errors

#10 | 2019-09-19
US20190287639A1
Physics

List insertion in test segments with non-naturally aligned data boundaries

#11 | 2019-06-27
US20190198132A1
Physics

List insertion in test segments with non-naturally aligned data boundaries

#12 | 2019-06-20
US20190188146A1
Physics

Method, system, and apparatus for stress testing memory translation tables

#13 | 2019-02-14
US20190050315A1
Physics

Efficient testing of direct memory address translation

#14 | 2019-02-14
US20190050314A1
Physics

Efficient testing of direct memory address translation

#15 | 2019-01-01
US15849597
Physics

Efficient testing of direct memory address translation

#16 | 2019-01-01
US15675717
Physics

Efficient testing of direct memory address translation

InventorID:

2430161 ⎘