Inventor profile of:

Scott E. Schaefer

City:

Boise, Idaho

Country:

United States

Published Applications:

148

Last publication date:

2026-05-21

Top Assignees for applications by Scott E. Schaefer

The entities that hold a legal rights for patent applications filed by inventor Schaefer Scott E.:

Recent patent applications by Schaefer Scott E.

Scott E. Schaefer from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-21
US20260141971A1
Physics

TEST MODE MONITORING AND FEEDBACK

#2 | 2026-05-14
US20260133708A1
Physics

SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST

#3 | 2026-03-05
US20260064534A1
Physics

COORDINATED ERROR CORRECTION

#4 | 2026-03-05
US20260064523A1
Physics

COORDINATED ERROR PROTECTION

#5 | 2026-01-22
US20260023648A1
Physics

EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC

#6 | 2026-01-15
US20260018230A1
Physics

TECHNIQUES FOR DETECTING A STATE OF A BUS

#7 | 2025-12-11
US20250377963A1
Physics

UNCORRECTABLE ERROR DETECTION IN MEMORY SYSTEMS

#8 | 2025-12-04
US20250370866A1
Physics

ON-DIE ERROR DETECTION AND CORRECTION FOR META DATA

#9 | 2025-12-04
US20250370865A1
Physics

COMMAND ADDRESS PARITY CHECK USING REPURPOSING

#10 | 2025-12-04
US20250370864A1
Physics

COMMAND ADDRESS PARITY CHECK USING A PARITY CHECK COMMAND

#11 | 2025-11-20
US20250355745A1
Physics

ALERT SIGNALING IN MEMORY SYSTEMS

#12 | 2025-10-23
US20250329406A1
Physics

INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKS

#13 | 2025-10-23
US20250328289A1
Physics

FREQUENCY MONITORING FOR MEMORY DEVICES

#14 | 2025-10-23
US20250328279A1
Physics

TECHNIQUES FOR DETECTING A STATE OF A BUS

#15 | 2025-10-16
US20250321829A1
Physics

ERROR CORRECTION MEMORY DEVICE WITH FAST DATA ACCESS

#16 | 2025-10-09
US20250315343A1
Physics

METHODS AND DEVICES FOR ERROR CORRECTION

#17 | 2025-10-02
US20250308616A1
Physics

INDICATING VALID MEMORY ACCESS OPERATIONS

#18 | 2025-09-25
US20250299763A1
Physics

INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST USING A DATA MASK INVERSION BIT

#19 | 2025-09-18
US20250292861A1
Physics

DIFFERENTIAL STROBE FAULT INDICATION

#20 | 2025-09-11
US20250284436A1
Physics

MEMORY COMMAND VERIFICATION

#21 | 2025-08-14
US20250258746A1
Physics

EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC

#22 | 2025-08-14
US20250258623A1
Physics

INTER-DEVICE COMMUNICATIONS FOR MEMORY HEALTH MONITORING

#23 | 2025-07-24
US20250238322A1
Physics

MEMORY DEVICE WITH STATUS FEEDBACK FOR ERROR CORRECTION

#24 | 2025-07-10
US20250226043A1
Physics

VALID WRITE OPERATION DETECTION FOR MEMORY DEVICES

#25 | 2025-07-10
US20250224884A1
Physics

SELF-REFRESH EXIT DETECTION FOR MEMORY DEVICES

#26 | 2025-06-26
US20250210122A1
Physics

MEMORY FAULT NOTIFICATION

#27 | 2025-06-19
US20250199710A1
Physics

OPERATIONAL MONITORING FOR MEMORY DEVICES

#28 | 2025-05-29
US20250173219A1
Physics

COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN

#29 | 2025-05-15
US20250158639A1
Electricity

ERROR DETECTION AND CLASSIFICATION AT A HOST DEVICE

#30 | 2025-05-15
US20250157514A1
Physics

MEMORY TRAFFIC MONITORING

#31 | 2025-04-10
US20250118388A1
Physics

METADATA STORAGE AT A MEMORY DEVICE

#32 | 2025-04-10
US20250117291A1
Physics

TARGETED COMMAND/ADDRESS PARITY LOW LIFT

#33 | 2025-03-06
US20250077345A1
Physics

HOST ERROR CONTROL MATRIX

#34 | 2025-02-27
US20250068515A1
Physics

INTERNAL ERROR CORRECTION FOR MEMORY DEVICES

#35 | 2025-02-06
US20250047304A1
Electricity

SYNDROME CHECK FUNCTIONALITY TO DIFFERENTIATE BETWEEN ERROR TYPES

#36 | 2025-02-06
US20250045157A1
Physics

REAL TIME SYNDROME CHECK

#37 | 2024-12-12
US20240412801A1
Physics

TECHNIQUES FOR DETECTING A STATE OF A BUS

#38 | 2024-12-05
US20240403155A1
Physics

ERROR LOG INDICATION VIA ERROR CONTROL INFORMATION

#39 | 2024-11-07
US20240372566A1
Electricity

SELECTIVE MODE ERROR CONTROL

#40 | 2024-10-31
US20240362134A1
Physics

RESOURCE ALLOCATION FOR A MEMORY BUILT-IN SELF-TEST

#41 | 2024-10-17
US20240347125A1
Physics

INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKS

#42 | 2024-10-17
US20240345932A1
Physics

MEMORY DEVICE HEALTH MONITORING LOGIC

#43 | 2024-10-10
US20240339170A1
Physics

INTERRUPTING A MEMORY BUILT-IN SELF-TEST

#44 | 2024-09-26
US20240320093A1
Physics

EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC

#45 | 2024-09-12
US20240303158A1
Physics

ERROR CORRECTION MEMORY DEVICE WITH FAST DATA ACCESS

#46 | 2024-09-12
US20240303157A1
Physics

MEMORY DIE FAULT DETECTION USING A CALIBRATION PIN

#47 | 2024-08-22
US20240282400A1
Physics

DIFFERENTIAL STROBE FAULT IDENTIFICATION

#48 | 2024-08-15
US20240274216A1
Physics

ENABLING OR DISABLING ON-DIE ERROR-CORRECTING CODE FOR A MEMORY BUILT-IN SELF-TEST

#49 | 2024-08-08
US20240265991A1
Physics

Bit retiring to mitigate bit errors

#50 | 2024-08-08
US20240264767A1
Physics

TECHNIQUES FOR DETECTING A STATE OF A BUS

#51 | 2024-08-01
US20240256187A1
Physics

TEMPERATURE MONITORING FOR MEMORY DEVICES

#52 | 2024-07-25
US20240250699A1
Electricity

MANAGING ERROR CONTROL INFORMATION USING A REGISTER

#53 | 2024-07-11
US20240232008A9
Physics

COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN

#54 | 2024-07-04
US20240220361A1
Physics

REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE

#55 | 2024-07-04
US20240220360A1
Physics

Targeted command/address parity low lift

#56 | 2024-07-04
US20240220354A1
Physics

COORDINATED ERROR PROTECTION

#57 | 2024-06-27
US20240211343A1
Physics

TECHNIQUES FOR INDICATING A WRITE LINK ERROR

#58 | 2024-06-20
US20240201908A1
Physics

Memory command verification

#59 | 2024-05-30
US20240176696A1
Physics

METHODS AND DEVICES FOR ERROR CORRECTION

#60 | 2024-04-25
US20240134744A1
Physics

Command address fault detection using a parity pin

#61 | 2024-04-18
US20240127902A1
Physics

Indicating a status of a memory built-in self-test

#62 | 2024-04-18
US20240126447A1
Physics

ADDRESS VERIFICATION AT A MEMORY DEVICE

#63 | 2024-04-11
US20240120947A1
Electricity

Error detection and classification at a host device

#64 | 2024-04-11
US20240118961A1
Physics

ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE

#65 | 2024-04-04
US20240111627A1
Physics

COORDINATED ERROR CORRECTION

#66 | 2024-04-04
US20240111626A1
Physics

Error status determination at a memory device

#67 | 2024-03-28
US20240103966A1
Physics

Redundancy-based error detection in a memory device

#68 | 2024-03-12
US18050679
Physics

Techniques for indicating a write link error

#69 | 2024-02-29
US20240069764A1
Physics

SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST

#70 | 2024-02-22
US20240061758A1
Physics

Resource allocation for a memory built-in self-test

#71 | 2024-02-08
US20240047004A1
Physics

Indicating a status of a memory built-in self-test for multiple memory device ranks

#72 | 2024-02-01
US20240038320A1
Physics

INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST USING A DATA MASK INVERSION BIT

#73 | 2024-01-25
US20240028454A1
Physics

Internal error correction for memory devices

#74 | 2023-12-28
US20230420065A1
Physics

Memory fault notification

#75 | 2023-12-28
US20230418708A1
Physics

Memory device with status feedback for error correction

#76 | 2023-12-21
US20230410933A1
Physics

Indicating a status of a memory built-in self-test

#77 | 2023-12-07
US20230395182A1
Physics

DIFFERENTIAL STROBE FAULT INDICATION

#78 | 2023-12-07
US20230395179A1
Physics

Interrupting a memory built-in self-test

#79 | 2023-12-07
US20230395177A1
Physics

Enabling or disabling on-die error-correcting code for a memory built-in self-test

#80 | 2023-12-07
US20230395174A1
Physics

Refresh rate selection for a memory built-in self-test

#81 | 2023-12-07
US20230395173A1
Physics

Memory section selection for a memory built-in self-test

#82 | 2023-12-07
US20230393935A1
Physics

Evaluation of memory device health monitoring logic

#83 | 2023-10-05
US20230315599A1
Physics

Evaluation of memory device health monitoring logic

#84 | 2023-07-20
US20230231574A1
Electricity

Syndrome check functionality to differentiate between error types

#85 | 2023-06-29
US20230205620A1
Physics

Coordinated error protection

#86 | 2023-06-22
US20230197182A1
Physics

Monitoring and adjusting access operations at a memory device

#87 | 2023-05-25
US20230161511A1
Physics

Command block management

#88 | 2023-05-25
US20230161491A1
Physics

Refresh counters in a memory system

#89 | 2023-05-11
US20230141845A1
Physics

Adaptive user defined health indication

#90 | 2023-03-09
US20230072766A1
Physics

Error log indication via error control information

#91 | 2023-03-02
US20230065593A1
Physics

Memory traffic monitoring

#92 | 2023-03-02
US20230063494A1
Physics

INDICATING VALID MEMORY ACCESS OPERATIONS

#93 | 2023-03-02
US20230062939A1
Electricity

Managing error control information using a register

#94 | 2023-03-02
US20230061144A1
Physics

Real time syndrome check

#95 | 2023-01-24
US17500751
Physics

Adaptive user defined health indication

#96 | 2023-01-19
US20230014955A1
Physics

Reset verification in a memory system

#97 | 2022-12-29
US20220414034A1
Physics

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

#98 | 2022-11-10
US20220358010A1
Physics

Internal error correction for memory devices

#99 | 2022-10-27
US20220342604A1
Physics

Memory device health evaluation at a host device

#100 | 2022-10-06
US20220317916A1
Physics

Inter-device communications for memory health monitoring

InventorID:

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