Inventor profile of:

Mike Violette

City:

Boise, Idaho

Country:

United States

Published Applications:

26

Last publication date:

2016-09-22

Top Assignees for applications by Mike Violette

The entities that hold a legal rights for patent applications filed by inventor Violette Mike:

Recent patent applications by Violette Mike

Mike Violette from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-09-22
US20160276409A1
Electricity

Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

#2 | 2014-08-21
US20140233300A1
Physics

Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

#3 | 2013-09-26
US20130248810A1
Electricity

Memory elements using self-aligned phase change material layers and methods of manufacturing same

#4 | 2013-05-16
US20130121056A1
Electricity

Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

#5 | 2012-11-08
US20120281466A1
Electricity

Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using same

#6 | 2012-09-06
US20120223285A1
Electricity

Resistive memory cell fabrication methods and devices

#7 | 2012-03-08
US20120056146A1
Electricity

Resistive memory architectures with multiple memory cells per access device

#8 | 2011-06-23
US20110149637A1
Physics

Method and apparatus providing high density chalcogenide-based data storage

#9 | 2011-03-17
US20110062409A1
Physics

Phase change memory structure with multiple resistance states and methods of programming and sensing same

#10 | 2010-12-23
US20100321992A1
Electricity

Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using same

#11 | 2010-09-16
US20100230654A1
Electricity

Resistive memory cell fabrication methods and devices

#12 | 2010-06-17
US20100151637A1
Electricity

Resistive memory architectures with multiple memory cells per access device

#13 | 2009-09-10
US20090225591A1
Physics

Resistive memory device

#14 | 2008-12-04
US20080298114A1
Physics

Phase change memory structure with multiple resistance states and methods of programming and sensing same

#15 | 2008-12-04
US20080298113A1
Electricity

Resistive memory architectures with multiple memory cells per access device

#16 | 2008-10-23
US20080258125A1
Electricity

Resistive memory cell fabrication methods and devices

#17 | 2008-06-05
US20080130353A1
Physics

Resistive memory device

#18 | 2008-02-21
US20080044632A1
Electricity

Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using

#19 | 2008-02-14
US20080037317A1
Physics

Resistive memory device

#20 | 2007-10-18
US20070242500A1
Physics

Method and apparatus providing high density data storage

#21 | 2006-10-19
US20060231902A1
Electricity

LOCOS trench isolation structures

#22 | 2005-12-01
US20050266666A1
Physics

Suppression of cross diffusion and gate depletion

#23 | 2005-11-08
US10659081
-

Suppression of cross diffusion and gate depletion

#24 | 2005-08-16
US10245679
-

Method of selectively forming local interconnects using design rules

#25 | 2005-05-31
US10780014
-

Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same

#26 | 2005-01-20
US20050012158A1
Electricity

Locos trench isolation structure

InventorID:

244947 ⎘