Austin, Texas
United States
30
2024-04-11
The entities that hold a legal rights for patent applications filed by inventor Plondke Erich:
Erich Plondke from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SINGLE INSTRUCTION MULTIPLE DATA (SIMD) SPARSE DECOMPRESSION WITH VARIABLE DENSITY
#2 | 2022-09-08VARIABLE QUANTIZATION FOR NEURAL NETWORKS
#3 | 2022-03-03Memory-bound scheduling
#4 | 2022-02-03REDUCED RESULT MATRIX
#5 | 2021-05-20Machine learning with input data domain transformation
#6 | 2020-04-30Constraining function approximation hardware integrated with fixed-point to floating-point conversion
#7 | 2019-11-21System and method of loading and replication of sub-vector values
#8 | 2019-06-27SYSTEM AND METHOD OF PRIORITY-BASED INTERRUPT STEERING
#9 | 2019-06-27System and method of floating point multiply operation processing
#10 | 2019-03-28System and method of feature descriptor processing
#11 | 2010-03-25System and method to execute a linear feedback-shift instruction
#12 | 2008-07-31Method and system to combine multiple register units within a microprocessor
#13 | 2008-02-21System and method of processing data using scalar/vector instructions
#14 | 2008-02-07Method and system to perform shifting and rounding operations within a microprocessor
#15 | 2008-01-17Method and system to indicate an exception-triggering page within a microprocessor
#16 | 2007-11-15Encoding hardware end loop information onto an instruction
#17 | 2007-04-26Pointer computation method and system for a scalable, programmable circular buffer
#18 | 2007-01-18Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor
#19 | 2006-12-28Shared translation look-aside buffer and method
#20 | 2006-10-26System and method of executing program threads in a multi-threaded processor
#21 | 2006-10-26Register files for a digital signal processor operating in an interleaved multi-threaded environment
#22 | 2006-10-12Multi-mode instruction memory unit
#23 | 2006-10-12System and method of using a predicate value to access a register file
#24 | 2006-10-12Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
#25 | 2006-10-05Mixed superscalar and VLIW instruction issuing and processing method and system
#26 | 2006-09-28Method and system for variable thread allocation and switching in a multithreaded processor
#27 | 2006-09-28Method and system for encoding variable length packets with variable instruction sizes
#28 | 2006-09-28Processor and method of indirect register read and write operations
#29 | 2006-09-21Processor and method of grouping and executing dependent instructions in a packet
#30 | 2006-09-14Variable interleaved multithreaded processor method and system
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