Berthold Reimer

Field-effect transistors with a grown silicon-germanium channel

Method of manufacturing a semiconductor wafer having an SOI configuration

METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS

SUPERIOR INTEGRITY OF A HIGH-K GATE STACK BY FORMING A CONTROLLED UNDERCUT ON THE BASIS OF A WET CHEMISTRY

Methods for etching dielectric materials in the fabrication of integrated circuits

Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions

Method of forming a semiconductor structure including a wet etch process for removing silicon nitride

TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE

Methods for PFET fabrication using APM solutions

Methods for pFET fabrication using APM solutions

Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer

Methods of controlling the etching of silicon nitride relative to silicon dioxide

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry

Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device

Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning

Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing