San Jose, California
United States
70
2018-10-11
The entities that hold a legal rights for patent applications filed by inventor Mitchell Craig:
Craig Mitchell from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Cavities containing multi-wiring structures and devices
#2 | 2018-09-13Warpage balancing in thin packages
#3 | 2018-09-06Microelectronic elements with post-assembly planarization
#4 | 2018-05-10Active chip on carrier or laminated chip having microelectronic element embedded therein
#5 | 2018-04-26Staged via formation from both sides of chip
#6 | 2018-02-08Warpage balancing in thin packages
#7 | 2017-10-12Reliable packaging and interconnect structures
#8 | 2017-09-07Microelectronic elements with post-assembly planarization
#9 | 2017-04-06ELECTRICAL BARRIER LAYERS
#10 | 2016-10-20Reliable packaging and interconnect structures
#11 | 2016-09-29Staged via formation from both sides of chip
#12 | 2016-08-11Laminated chip having microelectronic element embedded therein
#13 | 2016-06-09Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
#14 | 2015-11-19Electrical barrier layers
#15 | 2015-11-19Stacked microelectronic assembly with TSVs formed in stages with plural active chips
#16 | 2015-10-01Single exposure in multi-damascene process
#17 | 2015-09-03Microelectronic elements with post-assembly planarization
#18 | 2015-08-06Non-lithographic formation of three-dimensional conductive elements
#19 | 2015-07-02Reduced stress TSV and interposer structures
#20 | 2015-05-14Staged via formation from both sides of chip
#21 | 2015-04-16Cavities containing multi-wiring structures and devices
#22 | 2015-03-19THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE
#23 | 2015-01-22Multi-function and shielded 3D interconnects
#24 | 2014-11-20Compliant interconnects in wafers
#25 | 2014-10-30Reliable packaging and interconnect structures
#26 | 2014-08-07Reduced stress TSV and interposer structures
#27 | 2014-07-31Non-lithographic formation of three-dimensional conductive elements
#28 | 2014-07-24Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
#29 | 2014-07-24Active chip on carrier or laminated chip having microelectronic element embedded therein
#30 | 2014-06-12Reliable wire method
#31 | 2014-05-15Chip assembly having via interconnects joined by plating
#32 | 2014-04-10Compliant interconnects in wafers
#33 | 2014-04-10Multi-function and shielded 3D interconnects
#34 | 2014-03-27Reliable packaging and interconnect structures
#35 | 2014-02-27DUAL WAFER SPIN COATING
#36 | 2014-02-20Stacked microelectronic assembly with TSVS formed in stages with plural active chips
#37 | 2013-12-26Simultaneous wafer bonding and interconnect joining
#38 | 2013-12-12Reduced stress TSV and interposer structures
#39 | 2013-05-16Cavities containing multi-wiring structures and devices
#40 | 2013-01-17Connector structures and methods
#41 | 2013-01-17Electrical barrier layers
#42 | 2013-01-10Carrier structures for microelectronic elements
#43 | 2012-12-27Single exposure in multi-damascene process
#44 | 2012-12-27Reliable wire structure and method
#45 | 2012-12-20Reliable packaging and interconnect structures
#46 | 2012-11-01Three-dimensional system-in-a-package
#47 | 2012-08-09BSI image sensor package with variable-height silicon for even reception of different wavelengths
#48 | 2012-08-09BSI image sensor package with embedded absorber for even reception of different wavelengths
#49 | 2012-08-09BSI IMAGE SENSOR PACKAGE WITH VARIABLE LIGHT TRANSMISSION FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS
#50 | 2012-06-21Simultaneous wafer bonding and interconnect joining
#51 | 2012-06-21Void-free wafer bonding using channels
#52 | 2012-06-21Dual wafer spin coating
#53 | 2012-06-14Compliant interconnects in wafers
#54 | 2012-06-07Stacked microelectronic assembly with TSVs formed in stages with plural active chips
#55 | 2012-06-07Stacked microelectronic assembly having interposer connecting active chips
#56 | 2012-06-07Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
#57 | 2012-03-22Stacked chip assembly having vertical vias
#58 | 2012-03-22Chip assembly having via interconnects joined by plating
#59 | 2012-03-22Staged via formation from both sides of chip
#60 | 2012-03-22Multi-function and shielded 3D interconnects
#61 | 2012-01-26Microelectronic elements with post-assembly planarization
#62 | 2012-01-26Active chip on carrier or laminated chip having microelectronic element embedded therein
#63 | 2012-01-26Non-lithographic formation of three-dimensional conductive elements
#64 | 2012-01-26Methods of forming semiconductor elements using micro-abrasive particle stream
#65 | 2012-01-26Microelectronic elements having metallic pads overlying vias
#66 | 2012-01-26Microelectronic elements with rear contacts connected with via first or via middle structures
#67 | 2006-03-09Methods of making microelectronic assemblies including compliant interfaces
#68 | 2005-06-30Methods of making microelectronic assemblies including compliant interfaces
#69 | 2005-05-24Method of making a compliant integrated circuit package
#70 | 2005-03-22Methods of making microelectronic assemblies including compliant interfaces
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