Atul KATOCH

MEMORY DEVICE WITH GLOBAL AND LOCAL LATCHES

MEMORY DEVICE AND METHOD FOR FORMING THE SAME

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE

Far End Driver for Memory Clock

Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM

MEMORY DEVICE, READ CLOCK GENERATION CIRCUIT, AND METHOD FOR CONTROLLING READ OPERATION IN MEMORY DEVICE

MEMORY DEVICE WITH RESET VOLTAGE CONTROL

Semiconductor Device Including First and Second Clock Generators

METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES

MEMORY DEVICE WITH SIGNAL EDGE SHARPENER CIRCUITRY

Systems and Methods for Controlling Power Management Operations in a Memory Device

MEMORY DEVICE HAVING A COMPARATOR CIRCUIT

Robust Circuit for Negative Bit Line Generation in SRAM Cells

Memory device, read clock generation circuit, and method for controlling read operation in memory device

Semiconductor Device and Method of Operating the Same

Far End Driver for Memory Clock

Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM

VARIABLE VOLTAGE BIT LINE PRECHARGE

Method, device, and circuit for high-speed memories

MEMORY DEVICE WITH GLOBAL AND LOCAL LATCHES

LOW POWER WAKE UP FOR MEMORY

Global Boosting Circuit

Systems and methods for controlling power management operations in a memory device

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE

Word line delay interlock circuit for write operation

Memory device with reset voltage control

Method, device, and circuit for high-speed memories

Semiconductor device and method of operating the same

Bit line pre-charge circuit for power management modes in multi bank SRAM

Low power wake up for memory

Variable voltage bit line precharge

Robust circuit for negative bit line generation in SRAM cells

Semiconductor device including first and second clock generators

Memory device having a comparator circuit

Far end driver for memory clock

Memory device with global and local latches

Systems and methods for controlling power management operations in a memory device

Scan synchronous-write-through testing architectures for a memory device

Bit line pre-charge circuit for power management modes in multi bank SRAM

Systems and methods for controlling power management operations in a memory device

Word-line driver and method of operating a word-line driver

Memory device with signal edge sharpener circuitry

Memory device having a comparator circuit

Variable voltage bit line precharge

Memory device with global and local latches

Memory device with signal edge sharpener circuitry

SRAM with local bit line, input/output circuit, and global bit line

Scan synchronous-write-through testing architectures for a memory device

Word-line driver and method of operating a word-line driver

Memory architecture having first and second voltages

Word-line driver and method of operating a word-line driver

SRAM with local bit line, input/output circuit, and global bit line

Memory cell distance tracking circuits and methods

Memory device and compensation method therein

Scan synchronous-write-through testing architectures for a memory device

Memory array having disturb detector and write assistor

Memory architecture having first and second voltages

Word-line driver and method of operating a word-line driver

Memory circuit with assist circuit trimming

Memory controlling device by using multi-phase control signal and method thereof

Memory circuit with assist circuit trimming

Memory device with redundant IO circuit

Memory architecture and method of access thereto

Method of controlling a wordline

Memory architecture

Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same

Memory architecture having first and second voltages

Detecting write disturb in multi-port memories

Detecting write disturb in multi-port memories

Clamping circuit for multiple-port memory cell

Write assist circuit for write disturbed memory cell

Fault injection of finFET devices

Writing to multi-port memories

Read tracking mechanism

Power management during wakeup

Fault injection of finFET devices

Biasing bulk of a transistor

Sense amplifier

Tracking circuit

Memory architecture

Memory architecture

Memory circuits, systems, and methods for accessing the memory circuits

Boosting supply voltage

Wordline driver

Dual rail memory architecture

Sense amplifiers and exemplary applications

Pre-charge and equalization devices

VSS-sensing amplifier

Charge pump

Sense amplifier

Sense amplifier with adjustable back bias

VSS-sensing amplifier

Memory circuit with switch between sense amplifier and data line and method for operating the same

Memory circuits, systems, and methods for accessing the memory circuits

DATA COMMUNICATION METHOD, DATA TRANSMISSION AND RECEPTION DEVICE AND SYSTEM

Flash analog-to-digital converter

Integrated circuit, electronic device and integrated circuit control method