Inventor profile of:

Petra Leber

City:

Ehningen

Country:

Germany

Published Applications:

39

Last publication date:

2025-12-04

Top Assignees for applications by Petra Leber

The entities that hold a legal rights for patent applications filed by inventor Leber Petra:

Recent patent applications by Leber Petra

Petra Leber from Ehningen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-12-04
US20250370748A1
Physics

CONVERT INSTRUCTION WITH OVERFLOW RESULT CONTROL

#2 | 2025-10-23
US20250328346A1
Physics

INSTRUCTION WITH A PRESERVE SIGN CONTROL

#3 | 2025-10-02
US20250307124A1
Physics

VECTOR TEST ZONED INSTRUCTION FOR VALIDITY TESTING

#4 | 2025-10-02
US20250306921A1
Physics

VECTOR TEST DECIMAL INSTRUCTION FOR VALIDITY TESTING

#5 | 2025-09-30
US18618564
Physics

Vector test decimal instruction for validity testing

#6 | 2023-10-05
US20230315394A1
Physics

Verifying the correctness of a leading zero counter

#7 | 2023-10-05
US20230315386A1
Physics

Rounding hexadecimal floating point numbers using binary incrementors

#8 | 2023-09-28
US20230308113A1
Electricity

REDUCED LOGIC CONVERSION OF BINARY INTEGERS TO BINARY CODED DECIMALS

#9 | 2023-09-21
US20230297334A1
Physics

FLOATING-POINT CONVERSION WITH DENORMALIZATION

#10 | 2023-09-14
US20230289139A1
Physics

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

#11 | 2023-09-14
US20230289138A1
Physics

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

#12 | 2023-08-31
US20230273769A1
Physics

DYNAMIC ALGORITHM SELECTION

#13 | 2022-09-08
US20220283818A1
Physics

Hexadecimal floating point multiply and add instruction

#14 | 2022-09-01
US20220276867A1
Physics

Vector convert hexadecimal floating point to scaled decimal instruction

#15 | 2022-06-14
US17186302
Physics

Decimal scale and convert and split to hexadecimal floating point instruction

#16 | 2022-01-06
US20220004361A1
Physics

Repurposed hexadecimal floating point data path

#17 | 2021-03-11
US20210072989A1
Physics

Plausibility-driven fault detection in string termination logic for fast exact substring match

#18 | 2021-02-11
US20210042119A1
Physics

Efficient checking of a condition code anticipator for a floating point processor and/or unit

#19 | 2021-02-11
US20210042088A1
Physics

Condition code anticipator for hexadecimal floating point

#20 | 2021-02-04
US20210034325A1
Physics

Repurposed hexadecimal floating point data path

#21 | 2020-11-05
US20200348908A1
Physics

Hexadecimal exponent alignment for binary floating point unit

#22 | 2020-08-20
US20200264890A1
Physics

Digit validation check control in instruction execution

#23 | 2020-08-20
US20200264840A1
Physics

Negative zero control in instruction execution

#24 | 2020-08-06
US20200249982A1
Physics

Instruction interrupt suppression of overflow exception

#25 | 2020-02-27
US20200065097A1
Physics

Non-overlapping substring detection within a data element string

#26 | 2018-09-27
US20180276548A1
Physics

Residue prediction of packed data

#27 | 2018-09-27
US20180276547A1
Physics

Residue prediction of packed data

#28 | 2018-09-27
US20180276545A1
Physics

Residue prediction of packed data

#29 | 2018-07-19
US20180203670A1
Physics

Decimal floating point instructions to perform directly on compressed decimal floating point data

#30 | 2018-04-12
US20180101358A1
Physics

Decimal and binary floating point rounding

#31 | 2017-08-17
US20170235574A1
Physics

Inference based condition code generation

#32 | 2017-08-17
US20170235573A1
Physics

Inference based condition code generation

#33 | 2017-03-09
US20170068517A1
Physics

Decimal and binary floating point rounding

#34 | 2016-03-10
US20160070573A1
Physics

Inference based condition code generation

#35 | 2016-03-10
US20160070572A1
Physics

Inference based condition code generation

#36 | 2013-05-16
US20130124588A1
Physics

Encoding densely packed decimals

#37 | 2010-04-15
US20100095099A1
Physics

System and method for storing numbers in first and second formats in a register file

#38 | 2010-03-11
US20100063987A1
Physics

Supporting multiple formats in a floating point processor

#39 | 2010-03-04
US20100058266A1
Physics

3-stack floorplan for floating point unit

InventorID:

252016 ⎘