San Jose, California
United States
23
2025-12-25
The entities that hold a legal rights for patent applications filed by inventor Mateescu Robert Eugeniu:
Robert Eugeniu Mateescu from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
ARTIFICIAL INTELLIGENCE TRAINING SYSTEM
#2 | 2019-01-17Update efficient consensus protocols for erasure coded data stores
#3 | 2018-12-20Data recovery and regeneration using parity code
#4 | 2018-06-28Data mapping enabling fast read multi-level 3D NAND to improve lifetime capacity
#5 | 2018-06-14Cell-level realization of burn after reading for NAND flash
#6 | 2018-05-10System and methodology for low latency error management within a shared non-volatile memory architecture
#7 | 2017-07-06Distributed data storage with reduced storage overhead using reduced-dependency erasure codes
#8 | 2017-04-27Error location pointers for non volatile memory
#9 | 2017-03-30Joint decoding of rewriting NVM error sectors
#10 | 2016-04-07IMPLEMENTING ENHANCED PHASE CHANGE MEMORY (PCM) READ LATENCY THROUGH CODING
#11 | 2016-01-21Implementing enhanced performance with read before write to phase change memory to avoid write cancellations
#12 | 2015-05-21Implementing enhanced performance with read before write to phase change memory
#13 | 2014-06-12Techniques for storing bits in memory cells having stuck-at faults
#14 | 2014-06-12Techniques for encoding and decoding using a combinatorial number system
#15 | 2014-04-10Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults
#16 | 2014-04-10Encoding and decoding data to accommodate memory cells having stuck-at faults
#17 | 2013-09-19Shingled magnetic recording disk drive with inter-band disk cache and minimization of the effect of far track erasure on adjacent data bands
#18 | 2013-09-19Shingled magnetic recording disk drive with minimization of the effect of far track erasure on adjacent data bands
#19 | 2013-08-01Implementing enhanced data partial-erase for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding
#20 | 2013-08-01Implementing enhanced data read for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding
#21 | 2013-08-01Implementing enhanced data write for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding
#22 | 2013-05-16Techniques for storing data in stuck memory cells
#23 | 2013-05-16Techniques for storing data in stuck and unstable memory cells
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