David E. Lackey

Disposition of integrated circuits using performance sort ring oscillator and performance path testing

Test path selection and test program generation for performance testing integrated circuit chips

Microcontroller for logic built-in self test (LBIST)

Dense register array for enabling scan out observation of both L1 and L2 latches

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Design structure and apparatus for a robust embedded interface

Method and apparatus for a robust embedded interface

Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method

LSSD compatibility for GSD unified global clock buffers

CRITICAL PATH SELECTION FOR AT-SPEED TEST

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage

Apparatus and method for selectively implementing launch off scan capability in at speed testing

Method and device for selectively adding timing margin in an integrated circuit

Microcontroller for logic built-in self test (LBIST)

IC chip at-functional-speed testing with process coverage evaluation

METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

Negative edge flip-flops for muxscan and edge clock compatible LSSD

Testing of multiple asynchronous logic domains

Microcontroller for logic built-in self test (LBIST)

Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer

Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility

Voltage island chip implementation

Method for insertion of test points into integrated logic circuit designs

Pipeline array

Nested voltage island architecture