Stephen D. Wyatt

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Double data rate (DDR) memory read latency reduction

Circuit and method for on-chip jitter measurement

Structure for transforming an input voltage to obtain linearity between input and output functions and system and method thereof

Method and apparatus for dynamic characterization of reliability wearout mechanisms

Circuit and method for on-chip jitter measurement

Intrinsic RC power distribution for noise filtering of analog supplies

Structure for a high output resistance, wide swing charge pump

High output resistance, wide swing charge pump

Structure for intrinsic RC power distribution for noise filtering of analog supplies

Sub-picosecond multiphase clock generator

Circuit and method for on-chip jitter measurement

Intrinsic RC power distribution for noise filtering of analog supplies

Structure and method for providing gate leakage isolation locally within analog circuits

METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS

Performance measurement of device dedicated to phase locked loop using second order system approximation

Wide range crystal oscillator

Damping of LC ringing in IC (integrated circuit) power distribution systems

Leakage compensation circuit

Integrated circuit and method for interfacing two voltage domains using a transformer

System and method for control parameter re-centering in a controlled phase lock loop system