Allen, Texas
United States
17
2026-01-22
The entities that hold a legal rights for patent applications filed by inventor Chen Liang:
Liang Chen from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY WITH DATA BUS (DQ) MAPPINGS BASED ON FAULT BOUNDARY REQUIREMENTS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
#2 | 2025-03-20APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT
#3 | 2024-02-22Apparatuses and methods for a per-DRAM addressability synchronizer circuit
#4 | 2023-04-20Systems and methods for centralized address capture circuitry
#5 | 2023-04-06Command clock gate implementation with chip select signal training indication
#6 | 2022-06-09Write leveling a memory device using write DLL circuitry
#7 | 2020-06-09Timing circuit for command path in a memory device
#8 | 2020-03-12DFE conditioning for write operations of a memory device
#9 | 2019-12-26Write leveling a memory device
#10 | 2019-11-14Memory device with a signaling mechanism
#11 | 2019-10-22Write leveling a memory device
#12 | 2019-08-22Timing circuit for command path in a memory device
#13 | 2019-08-22Gap detection for consecutive write operations of a memory device
#14 | 2019-08-22DFE conditioning for write operations of a memory device
#15 | 2019-08-08DQS gating in a parallelizer of a memory device
#16 | 2019-08-06Memory device with a signaling mechanism
#17 | 2019-08-01Write level initialization synchronization
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