Cedar Park, Texas
United States
138
2022-11-17
The entities that hold a legal rights for patent applications filed by inventor Maule Warren E.:
Warren E. Maule from Cedar Park, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Hybrid memory mirroring using storage class memory
#2 | 2022-03-24Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
#3 | 2022-01-27Efficient and selective sparing of bits in memory systems
#4 | 2021-12-14Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
#5 | 2021-05-06Redundant voltage regulator for memory devices
#6 | 2020-07-16Efficient and selective sparing of bits in memory systems
#7 | 2020-03-26Common high and low random bit error correction logic
#8 | 2020-03-05Using dual channel memory as single channel memory with spares
#9 | 2020-01-09Redundant voltage regulator for memory devices
#10 | 2019-10-17Common high and low random bit error correction logic
#11 | 2019-08-15Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#12 | 2019-08-08Performing error correction in computer memory
#13 | 2019-07-25Efficient and selective sparing of bits in memory systems
#14 | 2019-07-18Tracking address ranges for computer memory errors
#15 | 2019-07-04Using dual channel memory as single channel memory with spares
#16 | 2019-07-04Using dual channel memory as single channel memory with command address recovery
#17 | 2019-06-20Redundant voltage regulator for memory devices
#18 | 2019-06-20Error correction potency improvement via added burst beats in a dram access cycle
#19 | 2019-06-20Three-dimensional stacked memory access optimization
#20 | 2019-06-20Three-dimensional stacked memory optimizations for latency and power
#21 | 2019-05-30Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#22 | 2019-05-30Host controlled data chip address sequencing for a distributed memory buffer system
#23 | 2019-03-14Memory mirror invocation upon detecting a correctable error
#24 | 2019-01-31Power management in multi-channel 3D stacked DRAM
#25 | 2019-01-31Power management in multi-channel 3D stacked DRAM
#26 | 2018-08-30Auto-disabling DRAM error checking on threshold
#27 | 2018-05-31Data buffer spare architectures for dual channel serial interface memories
#28 | 2018-03-15Efficient calibration of a data eye for memory devices
#29 | 2018-03-08Tracking address ranges for computer memory errors
#30 | 2018-03-08Confirming memory marks indicating an error in computer memory
#31 | 2018-03-08Performing error correction in computer memory
#32 | 2018-03-08Managing entries in a mark table of computer memory errors
#33 | 2018-02-27Data buffer spare architectures for dual channel serial interface memories
#34 | 2018-01-18Auto-disabling DRAM error checking on threshold
#35 | 2017-09-21Autonomous dram scrub and error counting
#36 | 2017-08-17Error monitoring of a memory device containing embedded error correction
#37 | 2017-06-22Efficient calibration of memory devices
#38 | 2017-06-01Efficient calibration of a data eye for memory devices
#39 | 2017-05-04Error monitoring of a memory device containing embedded error correction
#40 | 2017-04-27Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem
#41 | 2017-04-18Efficient calibration of a data eye for memory devices
#42 | 2017-04-11Efficient calibration of memory devices
#43 | 2017-03-02Nonvolatile memory data security
#44 | 2017-03-02Nonvolatile memory data security
#45 | 2017-03-02Selective memory error reporting
#46 | 2017-01-31Efficient calibration of a data eye for memory devices
#47 | 2016-11-24Adaptive error correction in a memory system
#48 | 2016-11-24Extended error correction coding data storage
#49 | 2016-11-24Extended error correction coding data storage
#50 | 2016-11-10Memory device error history bit
#51 | 2016-11-10Error vector readout from a memory device
#52 | 2016-11-10Error vector readout from a memory device
#53 | 2016-11-10Memory device error history bit
#54 | 2016-10-18Selective memory error reporting
#55 | 2016-08-18Detecting a cryogenic attack on a memory device with embedded error correction
#56 | 2016-08-04Error monitoring of a memory device containing embedded error correction
#57 | 2016-06-23Implementing DRAM row hammer avoidance
#58 | 2016-06-23Implementing DRAM row hammer avoidance
#59 | 2016-02-04Adaptive error correction in a memory system
#60 | 2016-02-04Adaptive error correction in a memory system
#61 | 2015-12-10Accessing a resistive memory storage device
#62 | 2015-10-13Accessing a resistive memory storage device
#63 | 2015-07-30Error feedback and logging with memory on-chip error checking and correcting (ECC)
#64 | 2015-07-30Error feedback and logging with memory on-chip error checking and correcting (ECC)
#65 | 2015-06-25Detecting defective connections in stacked memory devices
#66 | 2015-06-25Detecting defective connections in stacked memory devices
#67 | 2015-05-21Error-correcting code distribution for memory systems
#68 | 2015-04-23Implementing memory device with sub-bank architecture
#69 | 2015-03-26Implementing memory module communications with a host processor in multiported memory configurations
#70 | 2014-11-20MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE
#71 | 2014-08-07Securing the contents of a memory device
#72 | 2014-08-07Securing the contents of a memory device
#73 | 2014-05-01Implementing decoupling devices inside a TSV DRAM stack
#74 | 2014-04-24Memory system connector
#75 | 2014-04-24Implementing SDRAM having no RAS to CAS delay in write operation
#76 | 2013-11-28Implementing decoupling devices inside a TSV DRAM stack
#77 | 2013-05-23Memory system with dynamic refreshing
#78 | 2012-06-14Memory system with a programmable refresh cycle
#79 | 2012-01-26Memory system with delay locked loop (DLL) bypass control
#80 | 2011-01-06Method for enhancing the memory bandwidth available through a memory module
#81 | 2010-11-25System to improve miscorrection rates in error control code through buffering and associated methods
#82 | 2010-10-21Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
#83 | 2010-08-26High availability memory system
#84 | 2010-01-07Cascade interconnect memory system with enhanced reliability
#85 | 2010-01-07276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES
#86 | 2010-01-07276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES
#87 | 2010-01-07ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM
#88 | 2010-01-07ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM
#89 | 2010-01-07PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM
#90 | 2010-01-07276-pin buffered memory module with enhanced memory system interconnect and features
#91 | 2009-10-08System and method for providing a non-power-of-two burst length in a memory system
#92 | 2009-08-27Methods, systems, and computer program products for dynamic selective memory mirroring
#93 | 2009-08-06Partial cache line accesses based on memory access patterns
#94 | 2009-08-06Dynamic selection of a memory access size
#95 | 2009-08-06Interconnect operation indicating acceptability of partial data delivery
#96 | 2009-08-06Cache management for partial cache line operations
#97 | 2009-08-06Claiming coherency ownership of a partial cache line of data
#98 | 2009-07-30System for a combined error correction code and cyclic redundancy check code for a memory channel
#99 | 2009-07-30Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
#100 | 2009-07-30System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
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