Boeblingen
Germany
9
2020-04-23
The entities that hold a legal rights for patent applications filed by inventor Juchmes Werner:
Werner Juchmes from Boeblingen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
#2 | 2018-07-26Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
#3 | 2018-07-26Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
#4 | 2016-08-30Hierarchical negative bitline boost write assist for SRAM memory devices
#5 | 2016-04-07Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block
#6 | 2013-05-23REDUCED LEAKAGE BANKED WORDLINE HEADER
#7 | 2012-06-21Reduced power consumption memory circuitry
#8 | 2010-05-13Test interface for memory elements
#9 | 2009-07-07Bypass circuit for memory arrays
258986 ⎘