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Inventor profile of:

Sergio Schuler

City:

Austin, Texas

Country:

United States

Published Applications:

20

Last publication date:

2026-05-28

Top Assignees for applications by Sergio Schuler

The entities that hold a legal rights for patent applications filed by inventor Schuler Sergio:

Mythic, Inc. 10 Austin, TX United States
FREESCALE SEMICONDUCTOR, INC 3 Austin, TX United States
ARM Limited 2 Cambridge, United Kingdom
Mythic, Inc. 1 Round Rock, TX United States

Recent patent applications by Schuler Sergio

Sergio Schuler from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-28

US20260147576A1

ALTERNATIVE PREDICTION STORAGE

#2 | 2026-05-28

US20260147573A1

MULTI-TAKEN PREDICTION ENTRIES FOR PREDICTION RESUMPTION

#3 | 2026-05-28

US20260147572A1

SKIPPING PREDICTIONS ON A FLUSH

#4 | 2025-12-25

US20250390309A1

TECHNIQUE FOR GENERATING PREDICTIONS OF A TARGET ADDRESS OF BRANCH INSTRUCTIONS

#5 | 2024-09-19

US20240311194A1

TILE SUBSYSTEM AND METHOD FOR AUTOMATED DATA FLOW AND DATA PROCESSING WITHIN AN INTEGRATED CIRCUIT ARCHITECTURE

#6 | 2024-09-12

US20240303217A1

SYSTEMS AND METHODS FOR IMPLEMENTING AN INTELLIGENCE PROCESSING COMPUTING ARCHITECTURE

#7 | 2024-02-27

US17960390

Branch predictor triggering

#8 | 2022-09-01

US20220276983A1

Systems and methods for implementing an intelligence processing computing architecture

#9 | 2021-09-09

US20210280266A1

Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture

#10 | 2021-07-29

US20210232435A1

Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture

#11 | 2021-05-27

US20210158889A1

Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture

#12 | 2021-05-27

US20210157648A1

Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture

#13 | 2020-09-17

US20200293233A1

Apparatus and method for providing data to a master device

#14 | 2020-06-18

US20200192858A1

Systems and methods for implementing an intelligence processing computing architecture

#15 | 2020-01-09

US20200012617A1

Systems and methods for implementing an intelligence processing computing architecture

#16 | 2020-01-09

US20200012616A1

Systems and methods for implementing an intelligence processing computing architecture

#17 | 2009-10-01

US20090249048A1

BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR

#18 | 2008-11-13

US20080282251A1

Thread de-emphasis instruction for multithreaded processor

#19 | 2008-08-28

US20080209182A1

Multiple address and arithmetic bit-mode data processing device and methods thereof

#20 | 2008-04-03

US20080082843A1

Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch

InventorID:

2611244 ⎘