Inventor profile of:

Wei Wang

City:

Dublin, California

Country:

United States

Published Applications:

43

Last publication date:

2026-03-19

Top Assignees for applications by Wei Wang

The entities that hold a legal rights for patent applications filed by inventor Wang Wei:

Recent patent applications by Wang Wei

Wei Wang from Dublin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-19
US20260079828A1
Physics

MODEL BASED ERROR AVOIDANCE

#2 | 2026-03-05
US20260064526A1
Physics

MEMORY DEVICE BAD COLUMN IDENTIFICATION AND COMPENSATION

#3 | 2026-02-26
US20260056837A1
Physics

SELECTIVE CODEWORD MEDIA SCAN SYSTEM

#4 | 2025-11-20
US20250355573A1
Physics

BLOCK STRIPE BUILDING FOR A MEMORY DEVICE

#5 | 2025-10-30
US20250335101A1
Physics

HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-SYSTEM OPERATIONS

#6 | 2025-05-01
US20250138996A1
Physics

MODEL BASED ERROR AVOIDANCE

#7 | 2024-11-14
US20240377990A1
Physics

HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-SYSTEM OPERATIONS

#8 | 2024-10-03
US20240330717A1
Physics

MACHINE LEARNING-BASED ADJUSTMENT OF MEMORY CONFIGURATION PARAMETERS

#9 | 2024-09-26
US20240320077A1
Physics

ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION

#10 | 2024-06-13
US20240192875A1
Physics

REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM

#11 | 2024-03-28
US20240104030A1
Physics

Scheduling of read operations and write operations based on a data bus mode

#12 | 2024-02-22
US20240062839A1
Physics

Performing block-level media management operations for block stripes in a memory device

#13 | 2024-02-01
US20240037033A1
Physics

Managing power loss in a memory device

#14 | 2023-12-07
US20230393920A1
Physics

Adaptive wear leveling for endurance compensation

#15 | 2023-06-29
US20230207042A1
Physics

Detect whether die or channel is defective to confirm temperature data

#16 | 2023-04-27
US20230131347A1
Physics

MANAGING THERMAL THROTTLING IN A MEMORY SUB-SYSTEM

#17 | 2023-03-23
US20230090523A1
Physics

Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system

#18 | 2023-03-02
US20230065617A1
Physics

Managing power loss in a memory device

#19 | 2023-03-02
US20230062949A1
Physics

Rapid reliable file system access

#20 | 2023-02-23
US20230056938A1
Physics

Defect detection in memory based on active monitoring of read operations

#21 | 2022-12-06
US17445392
Physics

Defect detection in memory based on active monitoring of read operations

#22 | 2022-10-13
US20220326856A1
Physics

Scanning techniques for a media-management operation of a memory sub-system

#23 | 2022-09-08
US20220283744A1
Physics

Hardware based status collector acceleration engine for memory sub-system operations

#24 | 2022-05-19
US20220155840A1
Physics

Minimizing power loss and reset time with media controller suspend

#25 | 2022-03-31
US20220101940A1
Physics

Detect whether die or channel is defective to confirm temperature data

#26 | 2022-03-31
US20220100608A1
Physics

Power loss recovery for memory devices

#27 | 2022-03-31
US20220100605A1
Physics

Preemptive read verification after hardware write back

#28 | 2022-03-10
US20220075682A1
Physics

Reset and replay of memory sub-system controller in a memory sub-system

#29 | 2022-01-27
US20220027077A1
Physics

Managing an adjustable write-to-read delay of a memory sub-system

#30 | 2021-09-02
US20210271421A1
Physics

Double threshold controlled scheduling of memory access commands

#31 | 2021-03-25
US20210089476A1
Physics

Scheduling of read operations and write operations based on a data bus mode

#32 | 2021-03-11
US20210073068A1
Physics

Write buffer management

#33 | 2021-03-04
US20210064248A1
Physics

Scanning techniques for a media-management operation of a memory sub-system

#34 | 2021-01-21
US20210019218A1
Physics

Media management logger for a memory sub-system

#35 | 2021-01-21
US20210019217A1
Physics

Reset and replay of memory sub-system controller in a memory sub-system

#36 | 2021-01-21
US20210019182A1
Physics

Scheduling command execution

#37 | 2021-01-21
US20210019181A1
Physics

Internal management traffic regulation for memory sub-systems

#38 | 2021-01-21
US20210019089A1
Physics

Hardware based status collector acceleration engine for memory sub-system operations

#39 | 2021-01-21
US20210019051A1
Physics

HARDWARE BASED ACCELERATOR FOR MEMORY SUB-SYSTEM OPERATIONS

#40 | 2020-09-03
US20200278808A1
Physics

Double threshold controlled scheduling of memory access commands

#41 | 2020-03-19
US20200089629A1
Physics

Scheduling of read operations and write operations based on a data bus mode

#42 | 2020-01-23
US20200026595A1
Physics

Write buffer management

#43 | 2019-12-12
US20190378565A1
Physics

Method and apparatus for adaptive data retention management in non-volatile memory

InventorID:

2623486 ⎘