Inventor profile of:

Michael Grillberger

City:

Radebeul

Country:

Germany

Published Applications:

19

Last publication date:

2025-09-04

Top Assignees for applications by Michael Grillberger

The entities that hold a legal rights for patent applications filed by inventor Grillberger Michael:

Recent patent applications by Grillberger Michael

Michael Grillberger from Radebeul, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-09-04
US20250279349A1
Electricity

CAPACITIVE JUNCTION BETWEEN CONDUCTIVE LINE AND CONDUCTIVE PILLAR WITH METHODS TO FORM SAME

#2 | 2023-12-14
US20230402555A1
Electricity

REFLECTIVE SEMICONDUCTOR DEVICE WITH MIRROR ELEMENTS HAVING TWO OXIDE LAYERS OVER ALUMINUM LAYER, AND RELATED METHOD

#3 | 2016-06-30
US20160190104A1
Electricity

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

#4 | 2013-05-23
US20130130498A1
Electricity

REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS

#5 | 2012-03-15
US20120061818A1
Electricity

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

#6 | 2012-03-01
US20120051392A1
Electricity

Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems

#7 | 2012-03-01
US20120049350A1
Electricity

Stress reduction in chip packaging by using a low-temperature chip-package connection regime

#8 | 2012-01-05
US20120001343A1
Electricity

Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features

#9 | 2012-01-05
US20120001330A1
Electricity

Semiconductor device comprising through hole vias having a stress relaxation mechanism

#10 | 2011-12-01
US20110291299A1
Electricity

Stress reduction in chip packaging by a stress compensation region formed around the chip

#11 | 2011-10-06
US20110244632A1
Electricity

Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime

#12 | 2011-09-01
US20110209548A1
Electricity

Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contacts

#13 | 2010-10-07
US20100252828A1
Electricity

SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS

#14 | 2010-05-06
US20100109005A1
Electricity

SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR STRUCTURE FOR DIE INTERNAL MONITORING PURPOSES

#15 | 2010-03-04
US20100052147A1
Electricity

Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability

#16 | 2010-03-04
US20100052134A1
Electricity

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

#17 | 2009-12-03
US20090294921A1
Electricity

SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER

#18 | 2009-10-01
US20090243116A1
Electricity

Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

#19 | 2009-06-04
US20090140246A1
Electricity

Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices

InventorID:

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