Stefan Payer

Method to limit the time a semiconductor device operates above a maximum operating voltage

Verifying the correctness of a leading zero counter

Rounding hexadecimal floating point numbers using binary incrementors

REDUCED LOGIC CONVERSION OF BINARY INTEGERS TO BINARY CODED DECIMALS

FLOATING-POINT CONVERSION WITH DENORMALIZATION

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

HARDWARE DEVICE TO EXECUTE INSTRUCTION TO CONVERT INPUT VALUE FROM ONE DATA FORMAT TO ANOTHER DATA FORMAT

DYNAMIC ALGORITHM SELECTION

Hexadecimal floating point multiply and add instruction

Vector string search instruction

Plausability-driven fault detection in result logic and condition codes for fast exact substring match

Plausibility-driven fault detection in string termination logic for fast exact substring match

Parallel rounding for conversion from binary floating point to binary coded decimal

Parallelized rounding for decimal floating point to binary coded decimal conversion

Instruction scheduling during execution in a processor

Fault-tolerant clock gating

Integrated circuit control latch protection

Vector string search instruction

Method and apparatus for wiring multiple technology evaluation circuits

Non-overlapping substring detection within a data element string

Rapid substring detection within a data element string

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Rapid partial substring matching

Rapid character substring searching

Automated stressing and testing of semiconductor memory cells

Automated stressing and testing of semiconductor memory cells

Automatic built-in self test for memory arrays

Stressing and testing semiconductor memory cells