Luca NASSI

Allocation of store buffer entries

TAGGED-DATA PREDICTION

CANCELLING CACHE ALLOCATION TRANSACTIONS

TECHNIQUE FOR HANDLING PREFETCHING

REGISTER CLEARING

Cracking instructions into a plurality of micro-operations

REGISTER MAPPING

Technique for improving efficiency of data processing operations in an apparatus that employs register renaming

Register freeing latency

Controlling data allocation to storage circuitry

Micro-operation supply rate variation

Technique for controlling use of a cache to store prefetcher metadata

Cache eviction control for a private cache in an out-of-order data processing apparatus

CIRCUITRY AND METHOD

Data processing

Apparatus and method of dispatching instructions for execution clusters based on dependencies

Executing branch instructions following a speculation barrier instruction

Cache control circuitry and methods

Data processing apparatus with respective banked registers for exception levels

Bit processing involving bit-level permutation instructions or operations

Processing of a temporary-register-using instruction including determining whether to process a register move micro-operation for transferring data from a first register file to a second register file based on whether a temporary variable is still available in the second register file

Dynamic SIMD instruction issue target selection

Execution pipeline adaptation

Handling modifications to permitted program counter ranges in a data processing apparatus

Apparatus and method for storing source operands for operations

Apparatus and method for controlling branch prediction