Inventor profile of:

Daniel Brad WU

City:

Plano, Texas

Country:

United States

Published Applications:

22

Last publication date:

2026-04-02

Top Assignees for applications by Daniel Brad WU

The entities that hold a legal rights for patent applications filed by inventor WU Daniel Brad:

Recent patent applications by WU Daniel Brad

Daniel Brad WU from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-02
US20260093635A1
Physics

TRANSLATION LOOKASIDE BUFFER PREWARMING

#2 | 2026-03-26
US20260086898A1
Physics

PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY

#3 | 2025-10-30
US20250337233A1
Electricity

METHODS, SYSTEMS, AND APPARATUS TO MONITOR POWER ELECTRONICS

#4 | 2025-09-25
US20250298755A1
Physics

MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME

#5 | 2025-09-11
US20250284646A1
Physics

SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES

#6 | 2025-04-10
US20250117338A1
Physics

NON-STALLING, NON-BLOCKING TRANSLATION LOOKASIDE BUFFER INVALIDATION

#7 | 2024-08-22
US20240281329A1
Physics

WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY

#8 | 2024-06-27
US20240211414A1
Physics

MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME

#9 | 2024-06-06
US20240184715A1
Physics

TRANSLATION LOOKASIDE BUFFER PREWARMING

#10 | 2024-04-18
US20240126703A1
Physics

Software-hardware memory management modes

#11 | 2023-08-17
US20230259461A1
Physics

Non-stalling, non-blocking translation lookaside buffer invalidation

#12 | 2023-08-10
US20230254907A1
Electricity

PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY

#13 | 2023-06-22
US20230195658A1
Physics

Multichannel memory arbitration and interleaving scheme

#14 | 2023-01-19
US20230013270A1
Physics

Write control for read-modify-write operations in cache memory

#15 | 2022-11-24
US20220374358A1
Physics

Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure

#16 | 2022-05-19
US20220156149A1
Physics

Pipelined read-modify-write operations in cache memory

#17 | 2021-04-15
US20210109868A1
Physics

Software-hardware memory management modes

#18 | 2021-04-15
US20210109867A1
Physics

Non-stalling, non-blocking translation lookaside buffer invalidation

#19 | 2021-04-15
US20210109866A1
Physics

Translation lookaside buffer prewarming

#20 | 2020-11-26
US20200371918A1
Physics

Write control for read-modify-write operations in cache memory

#21 | 2020-11-26
US20200371877A1
Physics

Pipelined read-modify-write operations in cache memory

#22 | 2020-04-16
US20200117620A1
Physics

Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure

InventorID:

2702808 ⎘