Inventor profile of:

David Campbell

City:

Austin, Texas

Country:

United States

Published Applications:

26

Last publication date:

2023-11-16

Top Assignees for applications by David Campbell

The entities that hold a legal rights for patent applications filed by inventor Campbell David:

Recent patent applications by Campbell David

David Campbell from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-11-16
US20230367595A1
Physics

GATHER BUFFER MANAGEMENT FOR UNALIGNED AND GATHER LOAD OPERATIONS

#2 | 2023-03-02
US20230062909A1
Physics

Sleeping and waking-up address translation that conflicts with translation level of active page table walks

#3 | 2022-12-27
US17389012
Physics

Marking in-flight requests affected by translation entry invalidation in a data processing system

#4 | 2022-12-08
US20220391208A1
Physics

Sharing instruction cache lines between multiple threads

#5 | 2022-12-08
US20220391207A1
Physics

Sharing instruction cache footprint between multiple threads

#6 | 2022-09-29
US20220309001A1
Physics

Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers

#7 | 2022-09-29
US20220309000A1
Physics

Power optimized prefetching in set-associative translation lookaside buffer structure

#8 | 2022-09-15
US20220292028A1
Physics

Unified translation miss queue for multiple address translation modes

#9 | 2022-02-17
US20220050792A1
Physics

Determining page size via page table cache

#10 | 2022-02-08
US17120371
Physics

Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges

#11 | 2022-02-03
US20220035748A1
Physics

Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

#12 | 2021-10-28
US20210334214A1
Physics

Virtual cache synonym detection using alias tags

#13 | 2021-07-29
US20210232693A1
Physics

Process-based virtualization system for executing a secure application process

#14 | 2021-07-08
US20210209031A1
Physics

System and method for handling address translation invalidations using an address translation invalidation probe

#15 | 2021-06-24
US20210191866A1
Physics

Virtual cache tag renaming for synonym handling

#16 | 2021-02-18
US20210049107A1
Physics

Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes

#17 | 2020-08-27
US20200272557A1
Physics

Virtual cache mechanism for program break point register exception handling

#18 | 2020-08-06
US20200250099A1
Physics

Virtual cache synonym detection using alias tags

#19 | 2020-08-06
US20200250093A1
Physics

Virtual cache tag renaming for synonym handling

#20 | 2020-06-25
US20200201778A1
Physics

Methods and systems for verifying out-of-order page fault detection

#21 | 2020-06-18
US20200192817A1
Physics

Methods and systems for predicting virtual address

#22 | 2020-06-11
US20200183858A1
Physics

Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)

#23 | 2020-06-11
US20200183856A1
Physics

Buffer and methods for address translations in a processor

#24 | 2020-06-04
US20200174793A1
Physics

Performance optimized congruence class matching for multiple concurrent radix translations

#25 | 2020-04-30
US20200133881A1
Physics

Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes

#26 | 2020-04-14
US16210074
Physics

Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)

InventorID:

2717239 ⎘