Raleigh, North Carolina
United States
118
2026-01-01
The entities that hold a legal rights for patent applications filed by inventor Walker Robert M.:
Robert M. Walker from Raleigh, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PORT ARBITRATION
#2 | 2025-11-13ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS
#3 | 2025-07-10APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS
#4 | 2025-06-19MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY
#5 | 2025-03-06NON-DETERMINISTIC MEMORY PROTOCOL
#6 | 2025-02-27MEMORY SEARCHING COMPONENT
#7 | 2025-02-13BANK MAPPING FOR MEMORY
#8 | 2025-02-06MAINTAINING INTEGRITY OF A MEMORY COMPONENT
#9 | 2025-02-06WRITE OR STORE DRIVEN BUFFER CACHE MEMORY FOR A RAID-PROTECTED MEMORY
#10 | 2025-01-16MANAGING ACCESS GRANULARITY IN A CACHE OF A MEMORY SUB-SYSTEM
#11 | 2025-01-09COMMAND SCHEDULING COMPONENT FOR MEMORY
#12 | 2025-01-02MEMORY MODULE INTERFACES
#13 | 2025-01-02MEMORY PROTOCOL
#14 | 2024-12-12MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION
#15 | 2024-10-31PORT ARBITRATION
#16 | 2024-07-25MEMORY PROTOCOL
#17 | 2024-06-06Memory having internal processors and data communication methods in memory
#18 | 2024-05-30ACCESS TRACKING IN MEMORY
#19 | 2024-05-02Dynamically sized redundant write buffer with sector-based tracking
#20 | 2024-04-18Non-deterministic memory protocol
#21 | 2024-03-07Port arbitration
#22 | 2024-02-22Data temperature associated with TLB flush request
#23 | 2024-02-01BLOOM FILTER INTEGRATION INTO A CONTROLLER
#24 | 2024-01-25Memory module interfaces
#25 | 2023-12-07ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS
#26 | 2023-12-07Memory device security and row hammer mitigation
#27 | 2023-06-29Interleaved cache prefetching
#28 | 2023-06-15Prefetch data associated with TLB fill requests
#29 | 2023-03-30Dynamically sized redundant write buffer with sector-based tracking
#30 | 2023-03-30Outstanding transaction monitoring for memory sub-systems
#31 | 2023-03-23Database persistence
#32 | 2023-03-02Cold data identification
#33 | 2023-03-02Memory sub-system address mapping
#34 | 2023-03-02Memory sub-system tier allocation
#35 | 2023-03-02COMMAND RETRIEVAL AND ISSUANCE POLICY
#36 | 2023-03-02Access tracking in memory
#37 | 2023-03-02Interleaved cache prefetching
#38 | 2023-03-02Dynamic queue depth adjustment
#39 | 2023-03-02Command scheduling component for memory
#40 | 2023-02-09Memory searching component
#41 | 2022-12-15MEMORY PROTOCOL WITH PROGRAMMABLE BUFFER AND CACHE SIZE
#42 | 2022-12-15Non-deterministic memory protocol
#43 | 2022-11-24Command scheduling in a memory subsystem according to a selected scheduling ordering
#44 | 2022-11-03Memory having internal processors and data communication methods in memory
#45 | 2022-10-06Cache filter
#46 | 2022-09-29Enhanced duplicate write data tracking for cache memory
#47 | 2022-09-01Memory protocol
#48 | 2022-07-07Sector-based tracking for a page cache
#49 | 2022-05-19Transaction identification
#50 | 2022-05-12Data migration for memory operation
#51 | 2022-05-05Memory protocol
#52 | 2022-04-14Systems, devices, techniques, and methods for data migration
#53 | 2022-03-17Cache line data
#54 | 2022-03-10Memory searching component
#55 | 2022-02-17Systems, devices, and methods for data migration
#56 | 2022-01-27Enhanced duplicate write data tracking for cache memory
#57 | 2022-01-20Managing processing of memory commands in a memory subsystem with a high latency backing store
#58 | 2022-01-20Credit-based scheduling of memory commands
#59 | 2021-11-18Dynamically sized redundant write buffer with sector-based tracking
#60 | 2021-11-18Sector-based tracking for a page cache
#61 | 2021-11-16Managing memory commands in a memory subsystem by adjusting a maximum number of low priority commands in a DRAM controller
#62 | 2021-08-26Memory protocol with command priority
#63 | 2021-08-19Memory module interfaces
#64 | 2021-07-08Non-deterministic memory protocol
#65 | 2021-07-01Eviction of a cache line based on a modification of a sector of the cache line
#66 | 2021-05-27Dynamic access granularity in a cache media
#67 | 2021-04-15Command selection policy with read priority
#68 | 2021-03-25Low latency cache for non-volatile memory in a hybrid DIMM
#69 | 2021-02-25Command selection policy
#70 | 2020-12-03Data migration dynamic random access memory
#71 | 2020-09-03Eviction of a cache line based on a modification of a sector of the cache line
#72 | 2020-08-06Transaction identification
#73 | 2020-07-02Memory protocol
#74 | 2020-06-25Memory controller
#75 | 2020-06-25MODULE PROCESSING RESOURCE
#76 | 2020-06-25Memory module including a controller and interfaces for communicating with a host and another memory module
#77 | 2020-06-25Memory module interfaces
#78 | 2020-05-21Data migration dynamic random access memory
#79 | 2020-05-21Data migration for memory operation
#80 | 2020-05-21Systems, devices, and methods for data migration
#81 | 2020-05-21Systems, devices, techniques, and methods for data migration
#82 | 2020-04-23Memory protocol
#83 | 2020-04-23Non-deterministic memory protocol
#84 | 2020-04-16Data transfer for wear leveling with bank clusters
#85 | 2020-03-19Cache operations in a hybrid dual in-line memory module
#86 | 2020-02-27Cache in a non-volatile memory subsystem
#87 | 2020-02-13Media manager cache with integrated drift buffer
#88 | 2020-02-06Media manager cache eviction timer for reads and writes during resistivity drift
#89 | 2019-12-05Cache filter
#90 | 2019-10-17Command selection policy with read priority
#91 | 2019-10-17Command selection policy with read priority
#92 | 2019-09-12Cache architecture for comparing data on a single page
#93 | 2019-04-25Command selection policy
#94 | 2019-04-25Command selection policy
#95 | 2019-02-28CACHE BUFFER
#96 | 2019-02-28Cache line data
#97 | 2019-02-07Cache filter
#98 | 2018-12-20Controlling memory devices using a shared channel
#99 | 2018-12-20Non-deterministic memory protocol
#100 | 2018-10-11Transaction identification
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