Rexford, New York
United States
51
2024-06-27
The entities that hold a legal rights for patent applications filed by inventor Robison Robert:
Robert Robison from Rexford, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PRODUCING STRESS IN NANOSHEET TRANSISTOR CHANNELS
#2 | 2023-06-29COMPOSITE MATERIAL PHASE CHANGE MEMORY CELL
#3 | 2023-06-29CONFORMAL DIELECTRIC CAP FOR SUBTRACTIVE VIAS
#4 | 2023-06-08WRAPAROUND CONTACT WITH REDUCED DISTANCE TO CHANNEL
#5 | 2023-05-04STRESSED MATERIAL WITHIN GATE CUT REGION
#6 | 2023-03-30LOOPED LONG CHANNEL FIELD-EFFECT TRANSISTOR
#7 | 2023-03-30Top via process with damascene metal
#8 | 2023-03-02Self-aligned C-shaped vertical field effect transistor
#9 | 2023-03-02FET WITH REDUCED PARASITIC CAPACITANCE
#10 | 2023-01-26Top via cut fill process for line extension reduction
#11 | 2022-11-10Single-mask alternating line deposition
#12 | 2022-07-14TOP VIA ON SUBTRACTIVELY ETCHED CONDUCTIVE LINE
#13 | 2022-06-23High aspect ratio vias for integrated circuits
#14 | 2022-06-09Conductive lines with subtractive cuts
#15 | 2022-05-19Interconnects having spacers for improved top via critical dimension and overlay tolerance
#16 | 2022-04-28Stepped top via for via resistance reduction
#17 | 2022-04-07Fully aligned top vias
#18 | 2022-02-03Subtractive line with damascene second line type
#19 | 2022-01-27Top via interconnect having a line with a reduced bottom dimension
#20 | 2022-01-27Top via stack
#21 | 2022-01-06Top via with next level line selective growth
#22 | 2022-01-06Top via with damascene line and via
#23 | 2022-01-06ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION
#24 | 2021-12-09Well-controlled edge-to-edge spacing between adjacent interconnects
#25 | 2021-11-04Top via interconnect having a line with a reduced bottom dimension
#26 | 2021-11-04Barrier-less prefilled via formation
#27 | 2021-11-04Interconnects having spacers for improved top via critical dimension and overlay tolerance
#28 | 2021-10-21Etch stop layer removal for capacitance reduction in damascene top via integration
#29 | 2021-10-07Top via with next level line selective growth
#30 | 2021-09-30Self-aligned isolation for nanosheet transistor
#31 | 2021-09-30Double patterned lithography using spacer assisted cuts for patterning steps
#32 | 2021-09-23Top via on subtractively etched conductive line
#33 | 2021-09-16Magnetoresistive random-access memory device including magnetic tunnel junctions
#34 | 2021-09-16Topological qubit device
#35 | 2021-09-09Hybrid selective dielectric deposition for aligned via integration
#36 | 2021-09-09SELF-ALIGNED BLOCK VIA PATTERNING FOR DUAL DAMASCENE DOUBLE PATTERNED METAL LINES
#37 | 2021-08-26Line cut patterning using sacrificial material
#38 | 2021-08-19Barrier removal for conductor in top via integration scheme
#39 | 2021-08-12Single-mask alternating line deposition
#40 | 2021-08-12Stepped top via for via resistance reduction
#41 | 2021-07-29Top vias with subtractive line formation
#42 | 2021-07-29Top vias with selectively retained etch stops
#43 | 2021-07-22Conductive lines with subtractive cuts
#44 | 2021-07-22Barrier-less prefilled via formation
#45 | 2021-07-15Top via stack
#46 | 2021-07-15Top via with damascene line and via
#47 | 2021-07-08Patterning line cuts before line patterning using sacrificial fill material
#48 | 2021-05-13Fully aligned top vias
#49 | 2021-05-06Top via with hybrid metallization
#50 | 2021-02-11Top via interconnects with wrap around liner
#51 | 2020-05-14Source and drain contact cut last process to enable wrap-around-contact
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