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Inventor profile of:

Julia R. GREER

City:

Pasadena, California

Country:

United States

Published Applications:

Last publication date:

2023-01-26

Top Assignees for applications by Julia R. GREER

The entities that hold a legal rights for patent applications filed by inventor GREER Julia R.:

California Institute of Technology 10 Pasadena, CA United States
PALO ALTO RESEARCH CENTER INCORPORATED 2 Palo Alto, CA United States
THE CALIFORNIA INSTITUTE OF TECHNOLOGY 2 Pasadena, CA United States
nFugue 1 Beverly Hills, CA United States

Recent patent applications by GREER Julia R.

Julia R. GREER from Pasadena, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-01-26

US20230024854A1

Performing operations; transporting

Structured hydrogel membranes for fresh water harvesting

#2 | 2022-10-20

US20220336933A1

Electricity

DIRECT CURRENT SPECTROSCOPY (DCS) TECHNIQUE FOR IN-OPERANDO CELL DIAGNOSTICS AND ANISOTROPIC RESISTANCE MONITORING

#3 | 2022-10-06

US20220314183A1

Performing operations; transporting

3D PRINTING OF METAL CONTAINING STRUCTURES

#4 | 2022-09-08

US20220281164A1

Performing operations; transporting

Tiled porous architected compositions, methods of their making and methods of their use

#5 | 2021-11-04

US20210340334A1

Chemistry; metallurgy

Self-assembly of shell-based architected materials

#6 | 2020-05-21

US20200156035A1

Performing operations; transporting

3D printing of metal containing structures

#7 | 2012-08-16

US20120205656A1

Electricity

Thin-Film Electronic Devices Including Pre-Deformed Compliant Substrate

#8 | 2012-07-19

US20120181346A1

Chemistry; metallurgy

Nanotextured surfaces and related methods, systems, and uses

#9 | 2012-05-31

US20120135260A1

Chemistry; metallurgy

Fabrication of nano-twinned nanopillars

#10 | 2010-11-18

US20100291385A1

Performing operations; transporting

Fabrication of vertically aligned metallic nanopillars

#11 | 2010-11-11

US20100281963A1

Physics

Nanoindenter tip for uniaxial tension and compression testing

#12 | 2009-11-26

US20090289333A1

Electricity

Annealing a buffer layer for fabricating electronic devices on compliant substrates

InventorID:

2735477 ⎘