Gregory William Alexander

Cache line hold state for multiprocessing computing systems

SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE

RETURNING A CONTENTION INDICATOR WITH A FETCH REQUEST TO ALLOW AN INTERRUPTED OPERATION TO COMPLETE

TARGET CHIP-CONTROLLED DATA PREFETCH FOR ACCELERATOR SHARING

PARTIAL ARRAY SPARING IN A MEMORY

Cache governance in a computing environment with multiple processors

DEADLOCK AND HANG AVOIDANCE IN A LARGE DISTRIBUTED COMPUTER SYSTEM

Invalidity protection for shared cache lines

PROCESSOR CROSS-CORE CACHE LINE CONTENTION MANAGEMENT

CROSS-CORE INVALIDATION SNAPSHOT MANAGEMENT

Load reissuing using an alternate issue queue

Cache management using cache scope designation

Preventing extraneous messages when exiting core recovery

BIDIRECTIONAL RING-BASED INTERCONNECTION NETWORKS FOR MULTIPROCESSORS

Decentralized hot cache line tracking fairness mechanism

Hot line fairness mechanism favoring software forward progress

Multiprocessor system cache management with non-authority designation

Shadow pointer directory in an inclusive hierarchical cache

Preemptive tracking of remote requests for decentralized hot cache line fairness tracking

Final cache directory state indication

Special tracking pool enhancement for core local cache address invalidates

Lateral persistence directory states

Multiple copy scoping bits for cache memory

Post completion execution in an out-of-order processor design

Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data

Accounting for multiple pipeline depths in processor instrumentation

Instruction scheduling during execution in a processor

Making precise operand-store-compare predictions to avoid false dependencies

Store instruction to store instruction dependency

Post completion execution in an out-of-order processor design

Imprecise register dependency tracking

Offset-based mechanism for storage in global completion tables

Adjusting thread balancing in response to disruptive complex instruction

Store hit multiple load side register for preventing a subsequent store memory violation

Write power optimization for hardware employing pipe-based duplicate register files

REGISTER DEALLOCATION IN A PROCESSING SYSTEM