Inventor profile of:

Robert E. Jones

City:

Austin, Texas

Country:

United States

Published Applications:

21

Last publication date:

2014-11-13

Top Assignees for applications by Robert E. Jones

The entities that hold a legal rights for patent applications filed by inventor Jones Robert E.:

Recent patent applications by Jones Robert E.

Robert E. Jones from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2014-11-13
US20140332980A1
Electricity

Methods of forming 3-D circuits with integrated passive devices

#2 | 2013-06-06
US20130143367A1
Electricity

Methods of forming 3-D circuits with integrated passive devices

#3 | 2012-04-05
US20120080730A1
Physics

Semiconductor device with photonics

#4 | 2011-02-03
US20110027950A1
Electricity

METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR

#5 | 2011-01-18
US12543619
-

Method of making a vertical photodetector

#6 | 2010-11-04
US20100276735A1
Physics

Semiconductor device with photonics

#7 | 2010-05-27
US20100127345A1
Electricity

3-D circuits with integrated passive devices

#8 | 2009-04-02
US20090086524A1
Physics

Programmable ROM using two bonded strata

#9 | 2008-08-28
US20080206984A1
Electricity

Conductive via formation utilizing electroplating

#10 | 2008-08-28
US20080206934A1
Electricity

Forming semiconductor fins using a sacrificial fin

#11 | 2008-08-28
US20080206933A1
Electricity

Semiconductor fin integration using a sacrificial fin

#12 | 2008-07-31
US20080182379A1
Electricity

Semiconductor wafer with low-K dielectric layer and process for fabrication thereof

#13 | 2007-08-09
US20070181653A1
Performing operations; transporting

Magnetic alignment of integrated circuits to each other

#14 | 2007-07-26
US20070170585A1
Electricity

Composite integrated device and methods for forming thereof

#15 | 2007-06-14
US20070134891A1
Electricity

SOI active layer with different surface orientation

#16 | 2007-03-15
US20070057384A1
Electricity

Semiconductor stacked die/wafer configuration and packaging and method thereof

#17 | 2007-02-01
US20070023121A1
Performing operations; transporting

Fabrication of three dimensional integrated circuit employing multiple die panels

#18 | 2006-08-24
US20060189050A1
Electricity

Method of forming a semiconductor device and an optical device and structure thereof

#19 | 2006-07-11
US11092418
-

Dual metal gate electrode semiconductor fabrication process and structure thereof

#20 | 2005-10-20
US20050233562A1
Electricity

Method for forming a gate electrode having a metal

#21 | 2005-07-12
US10378348
-

Self-aligned magnetic clad write line and its method of formation

InventorID:

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