Raleigh, North Carolina
United States
58
2026-01-29
The entities that hold a legal rights for patent applications filed by inventor Walker Robert:
Robert Walker from Raleigh, US has applied for patents for these inventions. The list has both pending applications and granted patents:
DISTRIBUTED HYBRID BUFFER FOR MEMORY SYSTEMS
#2 | 2025-12-11FINITE TIME COUNTING PERIOD COUNTING OF INFINITE DATA STREAMS
#3 | 2025-08-21SUPPORT FOR DETERMINISTIC AND NON-DETERMINISTIC MEMORY INPUT/OUTPUT
#4 | 2025-06-12Write Request Buffer
#5 | 2024-08-22MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES
#6 | 2024-07-11MEMORY SUB-SYSTEM FOR SUPPORTING DETERMINISTIC AND NON-DETERMINISTIC COMMANDS BASED ON COMMAND EXPIRATION AND THE STATE OF THE INTERMEDIATE COMMAND QUEUE
#7 | 2023-06-22Memory-flow control register
#8 | 2023-06-22Response-based interconnect control
#9 | 2023-06-22Write request buffer capable of responding to read requests
#10 | 2023-05-25Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue
#11 | 2023-02-16Memory sub-system for decoding non-power-of-two addressable unit address boundaries
#12 | 2022-02-17Memory sub-system-bounded memory function
#13 | 2022-01-27Memory sub-system for increasing bandwidth for command scheduling
#14 | 2022-01-20Prefetch for data interface bridge
#15 | 2021-07-22Memory sub-system for decoding non-power-of-two addressable unit address boundaries
#16 | 2021-07-22Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue
#17 | 2021-05-27Memory sub-system-bounded memory function
#18 | 2021-03-18Channel depth adjustment in memory systems
#19 | 2021-02-11Apparatuses and methods for memory address translation during block migration using depth mapping table based on mapping state
#20 | 2020-09-17Systems and methods for memory system management
#21 | 2020-08-27Memory sub-system for decoding non-power-of-two addressable unit address boundaries
#22 | 2020-08-20Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue
#23 | 2020-02-27Memory sub-system for increasing bandwidth for command scheduling
#24 | 2019-12-10Memory sub-system supporting non-deterministic commands
#25 | 2019-12-05Conditional operation in an internal processor of a memory device
#26 | 2019-04-25Systems and methods for memory system management
#27 | 2018-11-08Methods for migrating information stored in memory using an intermediate depth map
#28 | 2018-10-18Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
#29 | 2017-06-15Conditional operation in an internal processor of a memory device
#30 | 2016-09-08Systems and methods for memory system management based on thermal information of a memory system
#31 | 2016-03-03Systems and methods for accessing memory
#32 | 2016-02-11Control of page access in memory
#33 | 2015-03-12Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
#34 | 2014-10-09Systems and methods for memory system management based on information of a memory system
#35 | 2014-09-18Systems and methods for memory system management based on thermal information of a memory system
#36 | 2014-09-18Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
#37 | 2014-09-11Control of page access in memory
#38 | 2014-07-24Systems and methods for accessing memory
#39 | 2013-11-28Internal processor buffer
#40 | 2013-06-06Control of page access in memory
#41 | 2012-12-13Configurable multi-port memory device and method thereof
#42 | 2012-11-15Communication between internal and external processors
#43 | 2012-10-25Channel depth adjustment in memory systems
#44 | 2012-09-13Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
#45 | 2011-09-08Rank select using a global select pin
#46 | 2010-12-09Conditional operation in an internal processor of a memory device
#47 | 2010-12-09Internal processor buffer
#48 | 2010-12-09Direct communication with a processor internal to a memory device
#49 | 2010-12-09Parallel processing and internal processors
#50 | 2010-12-09Communication between internal and external processors
#51 | 2010-12-09Control of page access in memory
#52 | 2010-11-04Configurable multi-port memory devices and methods
#53 | 2009-08-06Rank select using a global select pin
#54 | 2005-12-01Chip to chip interface
#55 | 2005-06-30Memory device controlled with user-defined commands
#56 | 2005-06-30Burst mode implementation in a memory device
#57 | 2005-06-09Chip to chip interface for encoding data and clock signals
#58 | 2005-06-09Chip to chip interface
278473 ⎘